Project F brings FPGAs to life with exciting open-source designs you can build on.
Learn more at projectf.io and follow @WillFlux for updates.
Image generated by an FPGA using the Ad Astra design from our FPGA Graphics series.
The Library includes handy Verilog designs from across Project F. From framebuffers and video output, to division and square root, rom and ram, and even drawing shapes.
See Library for details or learn about the background to the Library.
In this series, we explore graphics at the hardware level and get a feel for the power of FPGAs. If you're new to the series, start by reading FPGA Graphics.
- FPGA Graphics: Designs - Blog
- Pong: Designs - Blog
- Hardware Sprites: Designs - Blog
- Ad Astra: Designs - Blog
- Framebuffers: Designs - Blog
- Life on Screen: Designs - Blog
- Lines and Triangles: Designs - Blog
- 2D Shapes: Designs - Blog
- Animated Shapes: coming soon
A three-part introduction to FPGA development with Verilog; currently available for two boards: the Arty A7 and Nexys Video.
The third part will be available for the Nexys Video soon.
Maths & Algorithms is our next topic. Stay tuned for this series in 2021.
Our designs seek to be vendor-neutral, but some functionality requires support for vendor primitives. We currently support two FPGA architectures:
- XC7 - Xilinx Series 7 FPGAs, such as Spartan-7 and Arty-7
- iCE40 - Lattice iCE40 FPGAs, such as iCE40 UltraPlus
Porting to other architectures should be straightforward.
We’ll use a few choice features from SystemVerilog to make Verilog a little more pleasant. If you’re familiar with Verilog, you’ll have no trouble. All the SystemVerilog features used are compatible with recent versions of Verilator, Yosys, and Xilinx Vivado