Merge pull request #183 from VisorFolks/development

<1.3.2> Beryllium Release

.github/CODEOWNERS

@@ -0,0 +1,22 @@
+# Cyancore root
+*				@visorfolks/cc-arch-board
+
+# Akash Kollipara owns
+/mk/				@akashkollipara
+/src/arch/avr/			@akashkollipara
+/src/arch/riscv/		@akashkollipara
+/src/platform/mega_avr/		@akashkollipara
+/src/platform/sifive/		@akashkollipara
+/src/driver/			@akashkollipara
+/src/lib/			@akashkollipara
+/src/inlcude/			@akashkollipara
+/src/visor/			@akashkollipara
+
+# Mayuri Lokhande owns
+/src/arch/arm/			@MayuriLokhande
+/src/platform/pico/		@MayuriLokhande
+/src/visor/supervisor/		@MayuriLokhande
+
+# Pranjal Chanda owns
+/src/visor/			@pranjalchanda08
+/src/lib/libposix/		@pranjalchanda08

.vscode/c_cpp_properties.json

@@ -6,7 +6,7 @@
                 "${workspaceFolder}/src/**"
             ],
             "intelliSenseMode": "${default}",
-            "compilerPath": "",
+            "compilerPath": "/usr/bin/gcc",
             "cStandard": "gnu17",
             "cppStandard": "gnu++14"
         }

README.md

@@ -14,7 +14,7 @@
   </div>
 </body>
 
-> **Version (arch:2 | major:4 | minor:2): 1.3.1**
+> **Version (arch:2 | major:4 | minor:2): 1.3.2**
 
 [![GitHub CI](https://github.com/VisorFolks/cyancore/actions/workflows/github_ci.yml/badge.svg)](https://github.com/VisorFolks/cyancore/actions/workflows/github_ci.yml)
 [![Quality Gate Status](https://sonarcloud.io/api/project_badges/measure?project=VisorFolks_cyancore&metric=alert_status)](https://sonarcloud.io/summary/new_code?id=VisorFolks_cyancore)

projects/demo_avr/config.mk

@@ -17,3 +17,4 @@ BOOTMSGS	:= 0
 EARLYCON_SERIAL	:= 1
 CONSOLE_SERIAL	:= 1
 OBRDLED_ENABLE	:= 1
+TERRAKERN	:= 0

projects/demo_riscv/config.mk

@@ -17,3 +17,4 @@ BOOTMSGS        := 0
 EARLYCON_SERIAL	:= 1
 CONSOLE_SERIAL	:= 1
 OBRDLED_ENABLE	:= 1
+TERRAKERN	:= 0

projects/hifive1b_bl/config.mk

@@ -17,3 +17,4 @@ BOOTMSGS        := 1
 EARLYCON_SERIAL	:= 1
 CONSOLE_SERIAL	:= 0
 OBRDLED_ENABLE	:= 1
+TERRAKERN	:= 0

projects/project.template/config.mk

@@ -15,3 +15,4 @@ PLATFORM	:=
 SYSLOG_MEMBUF	:=
 EARLYCON_SERIAL	:=
 CONSOLE_SERIAL	:=
+TERRAKERN	:= 

src/arch/README.md

@@ -2,7 +2,9 @@
 
 Home directory for CPU architecture specific sources.
 
+> Note : The folder structure is intentionally kept with the current resolution. **Do not modify it!**
+
 #### Supported Architectures
 * AVR
-* ARM [Coming soon]
-* RISCV [Coming soon]
+* RISCV
+* ARM [Coming Soon]

src/arch/arm/32m/README.md

@@ -0,0 +1,8 @@
+# ARM - 32M
+
+Home directory for ARM-32M CPU
+
+#### Supported Variants
+* M0
+* M0+
+* M4

src/arch/arm/32m/common_v6_v7/supervisor/arch_vectors.c

@@ -0,0 +1,61 @@
+/*
+ * CYANCORE LICENSE
+ * Copyrights (C) 2022, Cyancore Team
+ *
+ * File Name		: arch_verctors.c
+ * Description		: This file consists of array of vector table
+ *			  specific to arm-m proile.
+ * Primary Author	: Akash Kollipara [[email protected]]
+ * Organisation		: Cyancore Core-Team
+ */
+
+#include <status.h>
+
+extern uint8_t _start_start;
+extern void init(void);
+#define proto_irq_func(x)	extern void int_##x(void)
+proto_irq_func(1);
+proto_irq_func(2);
+proto_irq_func(3);
+proto_irq_func(4);
+proto_irq_func(5);
+proto_irq_func(6);
+proto_irq_func(7);
+proto_irq_func(8);
+proto_irq_func(9);
+proto_irq_func(10);
+proto_irq_func(11);
+proto_irq_func(12);
+proto_irq_func(13);
+proto_irq_func(14);
+
+/**
+ * arch_vectors - Interrupt vector table defined as per arm-m spec
+ * @brief This is the array of interrupt/exception vectors defined
+ * by arm-v6/v7 spec. This is generic implementation and upon any
+ * irq/excep, these function will call common handler which will
+ * deref based on irq id and call respective handler.
+ */
+
+const void (*arch_vectors[N_IRQ+1](void)) _SECTION(".archvectors") =
+[
+	&_stack_start,		// Stack start value has higher address of stack
+				// with as assumption that stack grows towards
+				// lower address
+
+	&init,			// CPU entry address
+	&int_1,			// IRQ 1 -> NMI
+	&int_2,			// IRQ 2 -> HardFault
+	&int_3,			// IRQ 3 -> M-Manage
+	&int_4,			// IRQ 4 -> BusFault
+	&int_5,			// IRQ 5 -> UsageFault
+	&int_6,			// IRQ 6 -> N/A
+	&int_7,			// IRQ 7 -> DBG info
+	&int_8,			// IRQ 8 -> Debugger handler
+	&int_9,			// IRQ 9 -> N/A
+	&int_10,		// IRQ 10 -> SVC
+	&int_11,		// IRQ 11 -> Debug Monitor
+	&int_12,		// IRQ 12 -> N/A 
+	&int_13,		// IRQ 13 -> PendSV
+	&int_14,		// IRQ 14 -> SysTick
+];

src/arch/avr/8/common_5x_6/terravisor/arch.c

@@ -10,6 +10,8 @@
  */
 
 #include <stdint.h>
+#include <stdbool.h>
+#include <assert.h>
 #include <status.h>
 #include <syslog.h>
 #include <plat_arch.h>
@@ -97,3 +99,47 @@ void _NORETURN arch_panic_handler_callback()
 panic:
 	while(1) arch_wfi();
 }
+
+static cpu_sleep_t sleep_flag;
+
+/**
+ * arch_suspended_state_was
+ *
+ * @brief This function checks for the suspended state
+ * and returns true or false based on arg.
+ *
+ * @param[in] state: suspended state
+ * @return bool: True/False
+ */
+bool arch_suspended_state_was(cpu_sleep_t state)
+{
+	assert(state != resume);
+	if(!sleep_flag)
+		return false;
+	return (sleep_flag == state);
+}
+
+/**
+ * arch_signal_suspend
+ *
+ * @brief This function is intended to be called before
+ * cpu enters suspend state. By passing the state, we store
+ * and use to check while exiting resume routine
+ *
+ * @param[in] state: Suspend state of cpu
+ */
+void arch_signal_suspend(cpu_sleep_t state)
+{
+	sleep_flag = state;
+}
+
+/**
+ * arch_signal_resume
+ *
+ * @brief This function signals resume of cpu. It is intended
+ * to be called after exiting resume routine.
+ */
+void arch_signal_resume(void)
+{
+	sleep_flag = resume;
+}

src/arch/avr/8/common_5x_6/terravisor/asm.S

@@ -21,39 +21,17 @@
  * As per the abi spec of AVR5-8, r1 is always supposed to be 0.
  * Hence, r1 is reset to 0 and other are moved with r1.
  */
+.altmacro
+.macro clear_reg n
+	eor	r\n, r\n
+.endm
+
 function zero_reg
-	eor	r1, r1
-	mov	r0, r1
-	mov	r2, r1
-	mov	r3, r1
-	mov	r4, r1
-	mov	r5, r1
-	mov	r6, r1
-	mov	r7, r1
-	mov	r8, r1
-	mov	r9, r1
-	mov	r10, r1
-	mov	r11, r1
-	mov	r12, r1
-	mov	r13, r1
-	mov	r14, r1
-	mov	r15, r1
-	mov	r16, r1
-	mov	r17, r1
-	mov	r18, r1
-	mov	r19, r1
-	mov	r20, r1
-	mov	r21, r1
-	mov	r22, r1
-	mov	r23, r1
-	mov	r24, r1
-	mov	r25, r1
-	mov	r26, r1
-	mov	r27, r1
-	mov	r28, r1
-	mov	r29, r1
-	mov	r30, r1
-	mov	r31, r1
+.set i, 0
+.rept 32
+	clear_reg %i
+.set i, i+1
+.endr
 	ret
 
 function arch_panic_handler
@@ -144,6 +122,7 @@ function arch_panic_handler
  *
  * @param id - ID of the interrupt vector
  */
+.altmacro
 .macro INT id
 /**
  * int_(id) - Interrupt router function
@@ -180,63 +159,9 @@ function isr
  * functions will be retained and others are cleaned up.
  */
 /*==========< Interrupt router functions >==========*/
-INT 1
-INT 2
-INT 3
-INT 4
-INT 5
-INT 6
-INT 7
-INT 8
-INT 9
-INT 10
-INT 11
-INT 12
-INT 13
-INT 14
-INT 15
-INT 16
-INT 17
-INT 18
-INT 19
-INT 20
-INT 21
-INT 22
-INT 23
-INT 24
-INT 25
-INT 26
-INT 27
-INT 28
-INT 29
-INT 30
-INT 31
-INT 32
-INT 33
-INT 34
-INT 35
-INT 36
-INT 37
-INT 38
-INT 39
-INT 40
-INT 41
-INT 42
-INT 43
-INT 44
-INT 45
-INT 46
-INT 47
-INT 48
-INT 49
-INT 50
-INT 51
-INT 52
-INT 53
-INT 54
-INT 55
-INT 56
-INT 57
-INT 58
-INT 59
-INT 60
+
+.set i, 1
+.rept 60
+	INT %i
+.set i, i+1
+.endr

src/arch/avr/8/common_5x_6/terravisor/include/arch.h

@@ -15,6 +15,7 @@
 #include <plat_arch.h>
 #include <avr.h>
 #include <mmio.h>
+#include <resource.h>
 #include <machine_call.h>
 
 /**
@@ -112,3 +113,9 @@ static inline void arch_nop()
 #define arch_isb()	arch_nop()
 #define arch_dsb()	arch_nop()
 #define arch_dmb()	arch_nop()
+
+#ifdef _STDBOOL_H_
+bool arch_suspended_state_was(cpu_sleep_t);
+void arch_signal_suspend(cpu_sleep_t);
+void arch_signal_resume(void);
+#endif

src/arch/avr/8/common_5x_6/terravisor/include/avr.h

@@ -30,3 +30,10 @@ typedef uint8_t istate_t;
 context_frame_t *get_context_frame();
 void arch_panic_handler_callback();
 bool in_isr(void);
+
+static inline void arch_update_sp(uint16_t *p)
+{
+	uint16_t temp = (uint16_t) p;
+	MMIO8(SPL) = (uint8_t)(temp & 0xff);
+	MMIO8(SPH) = (uint8_t)((temp >> 8) & 0xff);
+}

src/arch/riscv/32/README.md

@@ -0,0 +1,7 @@
+# RV32
+
+Home directory for RV32 CPU
+
+#### Supported Variants
+* RV32I
+* RV32IMAC

src/arch/riscv/32/a/README.md

@@ -0,0 +1,6 @@
+# RV32 A-Extension
+_RISC-V Atomic extension support_
+
+* This is a generic atomic extension layer.
+* This directory consists of sources that involve use of atomic instructions.
+* If any other directory uses same function or has same intended funcationality, make sure to use "weak" function definitions.

src/arch/riscv/32/i/README.md

@@ -0,0 +1,7 @@
+# RV32 I-Extension (baseline)
+
+* Supports machine, supervisor and undermode as of the commit date.
+* Hypervisor aka background supervisor spec is still under development.
+
+#### Supported execution levels
+* Terravisor (machine layer)

src/arch/riscv/32/i/terravisor/README.md

@@ -0,0 +1,10 @@
+# RV32 I [Terravisor]
+
+* Home directory for RV32 Terravisor sources.
+* I being baseline for RV cores, this is a common directory.
+* For terravisor documentation please read [Terravisor README](../../../../../visor/terravisor/README.md)
+
+#### Highlights
+* Bootstrap routine is mostly in C
+* Reduced use of ASM
+* Exception handling is unified by updated "mtvec" reg with handler address