move documentation to pages

docs/_docs/100-design.md

@@ -1,6 +1,6 @@
 ---
 title: "Simple 8085 Computer Design"
-permalink: /docs/design
+permalink: /design
 excerpt: "Design of the Simple 8085 Computer"
 ---
 
@@ -44,13 +44,13 @@ The complete memory addressing circuit is shown below.  Normally, the RAM (0000-
 
 Note that the inverters used in the memory addressing circuit are 74LS14 Schmitt-trigger inverters.  This is simply because there were two inverters left over from the power-on reset circuit.  Standard inverters would work equally well here.
 
-![Reset-mode adressing](docs/images/reset-jump.png)
+![Reset-mode adressing](images/reset-jump.png)
 Reset-mode addressing is accomplished with a combination of hardware and software.  The hardware forces the ROM to be selected when in the RESET state.  This condition is maintained until _A15_ goes high.  The software requires that first instruction in the ROM be a jump to a ROM location.  In this implementation, it is a jump to the beginning of the Monitor at F000.  Before the jump is executed, the processor's PC is at 0000, but is executing code that is assembled to start at 8000.  The jump causes the PC to go from 0000 to F000, raising the A15 line and clearing the reset flip flop.  From this point, ROM and RAM are addressed normally, with RAM starting at 0000 and ROM at 8000.
 
-![Reset Trace](docs/images/reset-trace.png)
+![Reset Trace](images/reset-trace.png)
 The image above shows the reset jump circuit in action, as captured by the excellent [Saleae Logic Analyzer](http://www.saleae.com).  The numbers shown above the Read line are a decode of address lines A0..A7.
 
-> :page_facing_up: The [Debugging page](docs/debugging) has notes on debugging with a logic analyzer
+The [Debugging page](docs/debugging) has notes on debugging with a logic analyzer.
 
 The trace begins with the processor in reset, which has caused the reset flip-flop's output (Reset FF Q) to go high.  As the processor comes out of reset (seen by Reset Out falling), _ROMEN_ is asserted due to the Reset flip flop.  The first instruction read from ROM is a 3 byte jump instruction to F000.  This is read from the beginning of the ROM, which would normally be at address 8000, although the processor's PC is actually at 0000.  After the jump, _A15_ goes high, clearing the flip flop.  At this point, RAM and ROM are now addressed normally, using _A15_ low and high, respectively.
 

docs/_docs/200-build.md

@@ -4,13 +4,13 @@ permalink: /docs/build
 excerpt: "Simple 8085 build steps"
 ---
 
-[![Simple 8085](docs/images/simple8085-500.jpg)](docs/images/simple8085.jpg)
+[![Simple 8085](images/simple8085-500.jpg)](images/simple8085.jpg)
 
 Initially, the system was prototyped on a solderless breadboard in the hopes that some basic functionality could be proven before spinning a real PCB.  Starting with the 8085 chip, functionality was tested as new components were added.
 
 ### Step 1: Free-run Test
 
-[![free run schematic](docs/images/step1-free-run-sch-360.png)](docs/images/step1-free-run-sch.png)[![free run build](docs/images/step1-free-run-360.jpg)](docs/images/step1-free-run.jpg)
+[![free run schematic](images/step1-free-run-sch-360.png)](images/step1-free-run-sch.png)[![free run build](images/step1-free-run-360.jpg)](images/step1-free-run.jpg)
 
 The first test was to wire up the processor with pull-down resistors on the data lines, forcing it to read a NOP for every instruction read.  This cycles though the entire address range forever and proves the basic processor functionality.  If the test is working correctly, the _A15..A8_ address lines will all toggle, with _A14_ twice as fast as _A15_, _A13_ twice _A14_, and so on.  This can be observed with an oscilloscope or logic analyzer, or even an LED and resistor on the top address lines if a slower clock crystal is used.
 
@@ -26,7 +26,7 @@ The only parts needed for this are the 8085, clock crystal, and eight resistors
 
 ### Step 2: ROM
 
-[![rom led schematic](docs/images/step2-rom-led-sch-360.png)](docs/images/step2-rom-led-sch.png)[![rom led build](docs/images/step2-rom-led-360.jpg)](docs/images/step2-rom-led.jpg)
+[![rom led schematic](images/step2-rom-led-sch-360.png)](images/step2-rom-led-sch.png)[![rom led build](images/step2-rom-led-360.jpg)](images/step2-rom-led.jpg)
 
 The next test was to wire in the address/data latch and to connect the EEPROM.  An initial test program was loaded that blinks an LED from the SOD line.  The RESET button was also added at this point.
 
@@ -51,7 +51,7 @@ If the test above suceedes, basic ROM wiring has been verified.  A [second test
 
 ### Step 3: Serial Communications
 
-[![rom serial schematic](docs/images/step3-rom-serial-sch-360.png)](docs/images/step3-rom-serial-sch.png)[![rom serial build](docs/images/step3-rom-serial-360.jpg)](docs/images/step3-rom-serial.jpg)
+[![rom serial schematic](images/step3-rom-serial-sch-360.png)](images/step3-rom-serial-sch.png)[![rom serial build](images/step3-rom-serial-360.jpg)](images/step3-rom-serial.jpg)
 
 The next test, with the same basic hardware, was to wire in the FTDI chip to the SOD and bit-bang a character out as async serial data.  The [ROM serial test program](code/test3-rom-serial.asm) writes a continuous stream of the 'T' character to the serial port.
 
@@ -61,7 +61,7 @@ Note that this program uses timing loops that are dependent on the frequency of
 
 ### Step 4: RAM
 
-[![ram serial schematic](docs/images/step4-ram-serial-sch-360.png)](docs/images/step4-ram-serial-sch.png)[![rom serial build](docs/images/step4-ram-serial-360.jpg)](docs/images/step4-ram-serial.jpg)
+[![ram serial schematic](images/step4-ram-serial-sch-360.png)](images/step4-ram-serial-sch.png)[![rom serial build](images/step4-ram-serial-360.jpg)](images/step4-ram-serial.jpg)
 
 The next test was to wire in the RAM chip and modify the test program to write some characters to RAM and read them back before outputting them as serial data.  The reset circuit was also expanded to include the power-on reset in addition to the existing button.
 
@@ -87,10 +87,10 @@ Now that RAM is working, code development can be sped up with the use of the [He
 
 ### Step 5: Memory Addressing
 
-[![rom serial build](docs/images/step5-addressing-360.jpg)](docs/images/step5-addressing.jpg)
+[![rom serial build](images/step5-addressing-360.jpg)](images/step5-addressing.jpg)
 
 At this point, the processor, ROM, and RAM had all been proven, at least for simple operations.  The address decoding and power-on jump logic were then added to swap the RAM and ROM starting addresses, making them compatible with the Explorer/85.
 
 Rather than writing a new test, the entire Monitor ROM and Basic were loaded from the Explorer.  Incredibly enough, it worked.
-![Simple 8085 Output](docs/images/s85-output.png)
+![Simple 8085 Output](images/s85-output.png)