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Chisel instead of Verilog #5

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Chisel instead of Verilog

Chisel instead of Verilog #5

Workflow file for this run

.github/workflows/docs.yaml at 10e2d65
name: docs
on:
push:
workflow_dispatch:
jobs:
docs:
runs-on: ubuntu-24.04
steps:
- name: Checkout repo
uses: actions/checkout@v4
with:
submodules: recursive
- name: Setup JDK
uses: actions/setup-java@v4
with:
distribution: temurin
java-version: 17
cache: sbt
- uses: sbt/setup-sbt@v1
- name: generate Verilog
run: sbt run
- name: Build docs
uses: TinyTapeout/tt-gds-action/docs@tt09