Adapt for Wokwi projects

.github/workflows/gds.yaml

@@ -23,18 +23,6 @@ jobs:
       - name: Run Tiny Tapeout Precheck
         uses: TinyTapeout/tt-gds-action/precheck@tt06
 
-  gl_test:
-    needs: gds
-    runs-on: ubuntu-latest
-    steps:
-      - name: checkout repo
-        uses: actions/checkout@v3
-        with:
-          submodules: recursive
-
-      - name: GL test
-        uses: TinyTapeout/tt-gds-action/gl_test@tt06
-
   viewer:
     needs: gds
     runs-on: ubuntu-latest

.github/workflows/wokwi_test.yaml

@@ -0,0 +1,66 @@
+name: wokwi_test
+# either manually started, or on a schedule
+on: [ push, workflow_dispatch ]
+jobs:
+  wokwi_test:
+    # ubuntu
+    runs-on: ubuntu-latest
+    steps:
+    # need the repo checked out
+    - name: checkout repo
+      uses: actions/checkout@v3
+      with:
+        submodules: recursive
+
+    # install oss fpga tools
+    - name: install oss-cad-suite
+      uses: YosysHQ/setup-oss-cad-suite@v2
+      with:
+          python-override: true
+          github-token: ${{ secrets.GITHUB_TOKEN }}
+    - run: | 
+        yosys --version
+        iverilog -V
+        cocotb-config --libpython
+        cocotb-config --python-bin
+
+    - name: checkout tt tools repo
+      uses: actions/checkout@v3
+      with:
+        repository: tinytapeout/tt-support-tools
+        path: tt
+        ref: tt06
+
+    # need python and requirements
+    - name: setup python
+      uses: actions/setup-python@v4
+      with:
+        python-version: '3.10'
+    - run: pip install -r tt/requirements.txt
+
+    # fetch the truth table
+    - name: fetch Verilog and build config
+      run: ./tt/tt_tool.py --create-user-config
+
+    # does the wokwi project have a truthtable?
+    - name: Check the truthtable exists
+      id: check_files
+      uses: andstor/file-existence-action@v2
+      with:
+        files: "src/truthtable.md"
+
+    - name: test
+      if: steps.check_files.outputs.files_exists == 'true'
+      run: |
+        cd src
+        make clean
+        make
+        # make will return success even if the test fails, so check for failure in the results.xml
+        ! grep failure results.xml
+
+    - name: upload vcd
+      if: success() || failure()
+      uses: actions/upload-artifact@v3
+      with:
+          name: test-vcd
+          path: src/*.vcd

README.md

@@ -1,4 +1,4 @@
-![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/test/badge.svg)
+![](../../workflows/gds/badge.svg) ![](../../workflows/docs/badge.svg) ![](../../workflows/wokwi_test/badge.svg)
 
 # Tiny Tapeout Verilog Project Template
 
@@ -10,15 +10,6 @@ TinyTapeout is an educational project that aims to make it easier and cheaper th
 
 To learn more and get started, visit https://tinytapeout.com.
 
-## Verilog Projects
-
-1. Add your Verilog files to the `src` folder.
-2. Edit the [info.yaml](info.yaml) and update information about your project, paying special attention to the `source_files` and `top_module` properties.
-3. Edit [docs/info.md](docs/info.md) and add a description of your project.
-4. Optionally, add a testbench to the `test` folder. See [test/README.md](test/README.md) for more information.
-
-The GitHub action will automatically build the ASIC files using [OpenLane](https://www.zerotoasiccourse.com/terminology/openlane/).
-
 ## Enable GitHub actions to build the results page
 
 - [Enabling GitHub Pages](https://tinytapeout.com/faq/#my-github-action-is-failing-on-the-pages-part)

info.yaml

@@ -1,22 +1,16 @@
-# Tiny Tapeout project information
+# Tiny Tapeout project information (Wokwi project)
 project:
+  wokwi_id:     0       # Set this to the ID of your Wokwi project (the number from the project's URL)
   title:        ""      # Project title
   author:       ""      # Your name
   discord:      ""      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
   description:  ""      # One line description of what your project does
-  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
+  language:     "Wokwi" # other examples include SystemVerilog, Amaranth, VHDL, etc
   clock_hz:     0       # Clock frequency in Hz (or 0 if not applicable)
 
   # How many tiles your design occupies? A single tile is about 167x108 uM.
   tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
 
-  # Your top module name must start with "tt_um_". Make it unique by including your github username:
-  top_module:  "tt_um_example"
-
-  # List your project's source files here. Source files must be in ./src and you must list each source file separately, one per line:
-  source_files:        
-    - "project.v"
-
 # The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
 pinout:
   # Inputs

src/cells.v

@@ -0,0 +1,102 @@
+/* 
+This file provides the mapping from the Wokwi modules to Verilog HDL.
+
+It's only needed for Wokwi designs.
+*/
+
+`define default_netname none
+
+module buffer_cell (
+    input wire in,
+    output wire out
+    );
+    assign out = in;
+endmodule
+
+module and_cell (
+    input wire a,
+    input wire b,
+    output wire out
+    );
+
+    assign out = a & b;
+endmodule
+
+module or_cell (
+    input wire a,
+    input wire b,
+    output wire out
+    );
+
+    assign out = a | b;
+endmodule
+
+module xor_cell (
+    input wire a,
+    input wire b,
+    output wire out
+    );
+
+    assign out = a ^ b;
+endmodule
+
+module nand_cell (
+    input wire a,
+    input wire b,
+    output wire out
+    );
+
+    assign out = !(a&b);
+endmodule
+
+module not_cell (
+    input wire in,
+    output wire out
+    );
+
+    assign out = !in;
+endmodule
+
+module mux_cell (
+    input wire a,
+    input wire b,
+    input wire sel,
+    output wire out
+    );
+
+    assign out = sel ? b : a;
+endmodule
+
+module dff_cell (
+    input wire clk,
+    input wire d,
+    output reg q,
+    output wire notq
+    );
+
+    assign notq = !q;
+    always @(posedge clk)
+        q <= d;
+
+endmodule
+
+module dffsr_cell (
+    input wire clk,
+    input wire d,
+    input wire s,
+    input wire r,
+    output reg q,
+    output wire notq
+    );
+
+    assign notq = !q;
+
+    always @(posedge clk or posedge s or posedge r) begin
+        if (r)
+            q <= 0;
+        else if (s)
+            q <= 1;
+        else
+            q <= d;
+    end
+endmodule