- Only Python >= 3.7 support
- Use GHA for CI
- Add split data bus module #145 #151 #153
- Add basic Verilotor support #146 #148 #149 #150
- Fix bug and compatibility issues of SHT85 driver
- Use NBA for the clock divider #156
- Signature support #158
- Update and improve seq_rec, seq_gen and jtag_master modules #161 #162 (it will not work with ISE)
- Update simulation framework #163