ENH: use module level logging, addressing #78

basil/HL/FEI4AdapterCard.py

@@ -15,6 +15,8 @@
 
 from basil.HL.HardwareLayer import HardwareLayer
 
+logger = logging.getLogger(__name__)
+
 
 class AdcMax1239(HardwareLayer):
     '''ADC MAX1238/MAX1239
@@ -327,9 +329,9 @@ def init(self):
         # read calibration
         if not self._init['no_calibration']:
             self.read_eeprom_calibration()
-            logging.info('Found adapter card: {}'.format('%s with ID %s' % ('Single Chip Adapter Card', self.get_id())))
+            logger.info('Found adapter card: {}'.format('%s with ID %s' % ('Single Chip Adapter Card', self.get_id())))
         else:
-            logging.info('FEI4AdapterCard: Skeeping calibration.')
+            logger.info('FEI4AdapterCard: Skeeping calibration.')
 
     def read_eeprom_calibration(self, temperature=False):  # use default values for temperature, EEPROM values are usually not calibrated and random
         '''Reading EEPROM calibration for power regulators and temperature

basil/HL/FEI4QuadModuleAdapterCard.py

@@ -15,6 +15,8 @@
 from basil.HL.HardwareLayer import HardwareLayer
 from basil.HL.FEI4AdapterCard import AdcMax1239, Eeprom24Lc128, Fei4Dcs
 
+logger = logging.getLogger(__name__)
+
 
 class DacMax5380(HardwareLayer):
     '''DAC MAX5380
@@ -148,7 +150,7 @@ def init(self):
         self._setup_adc(self.SETUP_FLAGS_BI)
         self.read_eeprom_calibration()
         self.set_current_limit('CH1', 1.0)
-        logging.info('Found adapter card: {}'.format('%s with ID %s' % ('Quad Module Adapter Card', self.get_id())))
+        logger.info('Found adapter card: {}'.format('%s with ID %s' % ('Quad Module Adapter Card', self.get_id())))
 
     def read_eeprom_calibration(self, temperature=False):  # use default values for temperature, EEPROM values are usually not calibrated and random
         '''Reading EEPROM calibration for power regulators and temperature

basil/HL/FadcConf.py

@@ -7,6 +7,8 @@
 from basil.HL.RegisterHardwareLayer import HardwareLayer
 import logging
 
+logger = logging.getLogger(__name__)
+
 
 class FadcConf(HardwareLayer):
 
@@ -15,7 +17,7 @@ def __init__(self, intf, conf):
 
     def init(self):
         super(FadcConf, self).init()
-        logging.info("Initializing FADC Configuration...")
+        logger.info("Initializing FADC Configuration...")
 
         self._intf.set_data([0x00, 0x10])  # RESET ADC
         self._intf.start()

basil/HL/GPAC.py

@@ -15,6 +15,8 @@
 from basil.HL.HardwareLayer import HardwareLayer
 from basil.HL.FEI4AdapterCard import Eeprom24Lc128
 
+logger = logging.getLogger(__name__)
+
 
 class MuxPca9540B(HardwareLayer):
     '''PCA 9540B
@@ -702,9 +704,9 @@ def init(self):
         # read calibration
         if not self._init['no_calibration']:
             self.read_eeprom_calibration()
-            logging.info('Found adapter card: {}'.format('%s with ID %s' % ('General Purpose Analog Card', self.get_id())))
+            logger.info('Found adapter card: {}'.format('%s with ID %s' % ('General Purpose Analog Card', self.get_id())))
         else:
-            logging.info('GPAC: Skeeping calibration.')
+            logger.info('GPAC: Skeeping calibration.')
 
         # setup current limit and current source
         self.set_current_limit('PWR0', 0.1)
@@ -882,5 +884,5 @@ def _set_dac_value(self, channel, value):
         # if value is greater than maximum dac value, set it to maximum and output an error message
         if value > 4095:
             value = 4095
-            logging.warning('%s DAC value reached maximum value', channel)
+            logger.warning('%s DAC value reached maximum value', channel)
         I2cAnalogChannel._set_dac_value(self, value=value, **self._ch_map[channel]['DAC'])

basil/HL/MIO_PLL.py

@@ -9,6 +9,8 @@
 
 from basil.HL.HardwareLayer import HardwareLayer
 
+logger = logging.getLogger(__name__)
+
 
 class MIO_PLL(HardwareLayer):
     '''
@@ -171,9 +173,9 @@ def _calculateParameters(self, fout):
                                             self.chg_pump = 4;
                         ftest = self.fref * self.p_total / self.q_total * 1 / self.div
                         fvco  = self.fref * self.p_total / self.q_total
-                        logging.info('PLL frequency set to ' + str(ftest) + ' MHz' + ' (VCO @ ' + str(fvco) + ' MHz)')
+                        logger.info('PLL frequency set to ' + str(ftest) + ' MHz' + ' (VCO @ ' + str(fvco) + ' MHz)')
                         return True
-        logging.error('MIO_PLL: Could not find PLL parameters')
+        logger.error('MIO_PLL: Could not find PLL parameters')
         return False
 
     def _updateRegisters(self):

basil/HL/NTCRegister.py

@@ -11,6 +11,8 @@
 
 from basil.HL.RegisterHardwareLayer import HardwareLayer
 
+logger = logging.getLogger(__name__)
+
 
 class NTCRegister(HardwareLayer):
     """ Register class for NTCRegister
@@ -31,7 +33,7 @@ def init(self):
         if "NTC_type" not in self._conf:
             self._conf["NTC_type"] = "TDK_NTCG16H"
 
-        logging.debug("Initializing NTC " + self._conf["NTC_type"] + " on channel " + self._conf["arg_add"]["channel"])
+        logger.debug("Initializing NTC " + self._conf["NTC_type"] + " on channel " + self._conf["arg_add"]["channel"])
 
         if self._conf["NTC_type"] == "TDK_NTCG16H":
             self.R_RATIO = np.array([18.85, 14.429, 11.133, 8.656, 6.779, 5.346, 4.245, 3.393, 2.728, 2.207, 1.796, 1.47, 1.209, 1.0, 0.831, 0.694, 0.583, 0.491, 0.416, 0.354, 0.302, 0.259, 0.223, 0.192, 0.167, 0.145, 0.127, 0.111, 0.0975, 0.086, 0.076, 0.0674, 0.0599, 0.0534])
@@ -60,7 +62,7 @@ def get_temperature(self, unit="K"):
             j = arg[0]
 
         k = 1.0 / (math.log(r_ratio / self.R_RATIO[j]) / self.B_CONST[j] + 1 / self.TEMP[j])[0]
-        logging.info("Temperature (C): %f", k - 273.15)
+        logger.info("Temperature (C): %f", k - 273.15)
 
         if unit == "C":
             return k - 273.15

basil/HL/RegisterHardwareLayer.py

@@ -14,6 +14,8 @@
 from basil.utils.BitLogic import BitLogic
 from basil.HL.HardwareLayer import HardwareLayer
 
+logger = logging.getLogger(__name__)
+
 
 # description attributes
 read_only = ['read_only', 'read-only', 'readonly', 'ro']
@@ -60,7 +62,7 @@ def init(self):
             version = str(self.VERSION)
         else:
             version = None
-        logging.debug("Initializing %s (firmware version: %s), module %s, base_addr %s" % (self.name, version if 'VERSION' in self._registers else 'n/a', self.__class__.__module__, hex(self._base_addr)))
+        logger.debug("Initializing %s (firmware version: %s), module %s, base_addr %s" % (self.name, version if 'VERSION' in self._registers else 'n/a', self.__class__.__module__, hex(self._base_addr)))
         if self._require_version and not eval(version + self._require_version):
             raise Exception("FPGA module %s does not satisfy version requirements (read: %s, require: %s)" % (self.__class__.__module__, version, self._require_version.strip()))
         for reg, value in self._registers.iteritems():
@@ -188,14 +190,14 @@ def getter(self):
             try:
                 return self._get(attribute)
             except Exception, e:
-                logging.error(e)
+                logger.error(e)
                 return None
 
         def setter(self, value):
             try:
                 return self._set(attribute, value)
             except Exception, e:
-                logging.error(e)
+                logger.error(e)
                 return None
         # construct property attribute and add it to the class
         setattr(self.__class__, attribute, property(fget=getter, fset=setter, doc=attribute + ' register'))

basil/HL/bram_fifo.py

@@ -12,6 +12,8 @@
 
 from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer
 
+logger = logging.getLogger(__name__)
+
 
 class bram_fifo(RegisterHardwareLayer):
     '''BRAM FIFO controller interface for bram_fifo FPGA module.
@@ -67,7 +69,7 @@ def get_data(self):
         fifo_int_size_2 = self.FIFO_INT_SIZE
         if fifo_int_size_1 > fifo_int_size_2:
             fifo_int_size = fifo_int_size_2  # use smaller chunk
-            logging.warning("Reading wrong FIFO size. Expected: %d <= %d" % (fifo_int_size_1, fifo_int_size_2))
+            logger.warning("Reading wrong FIFO size. Expected: %d <= %d" % (fifo_int_size_1, fifo_int_size_2))
         else:
             fifo_int_size = fifo_int_size_1  # use smaller chunk
         return np.frombuffer(self._intf.read(self._conf['base_data_addr'], size=4 * fifo_int_size), dtype=np.dtype('<u4'))  # size in number of bytes

basil/HL/iseg_shq.py

@@ -11,6 +11,8 @@
 
 from basil.HL.HardwareLayer import HardwareLayer
 
+logger = logging.getLogger(__name__)
+
 
 class IsegShq(HardwareLayer):
     '''Python interface for ISEG SHQ series
@@ -69,7 +71,7 @@ def set_voltage(self, channel, value=0, unit='V', ramp_speed=None):
         if ramp_speed:
             self.write_v_ramp(self, channel=channel, ramp_speed=ramp_speed)
         self.iseg.write_v_set(channel, raw)
-        logging.info('Ramping voltage...')
+        logger.info('Ramping voltage...')
         self.iseg.write_start_ramp(channel)
         while True:
             status = self.iseg.read_status_word(channel=channel)
@@ -78,9 +80,9 @@ def set_voltage(self, channel, value=0, unit='V', ramp_speed=None):
             elif status == 'ON':
                 break
             else:
-                logging.warning('CH%d: ramping voltage failed with status %s (%s)', channel, status, status_words[status])
+                logger.warning('CH%d: ramping voltage failed with status %s (%s)', channel, status, status_words[status])
                 break
-        logging.info('Finished ramping voltage')
+        logger.info('Finished ramping voltage')
 
     def get_voltage(self, channel, unit='V'):
         raw = self.iseg.read_voltage(channel)
@@ -115,6 +117,6 @@ def trip_reset(self, channel):
             if status == 'ON' or status == 'OFF':
                 break
             if loop_cnt >= 3:
-                logging.warning('CH%d: status %s (%s) after trip reset', channel, status, status_words[status])
+                logger.warning('CH%d: status %s (%s) after trip reset', channel, status, status_words[status])
                 break
             loop_cnt += 1

basil/HL/mercury.py

@@ -4,8 +4,6 @@
 # SiLab, Institute of Physics, University of Bonn
 # ------------------------------------------------------------
 #
-import logging
-
 from basil.HL.RegisterHardwareLayer import HardwareLayer
 
 

basil/HL/sitcp_fifo.py

@@ -4,9 +4,6 @@
 # SiLab, Institute of Physics, University of Bonn
 # ------------------------------------------------------------
 #
-
-import logging
-
 import numpy as np
 
 from basil.HL.HardwareLayer import HardwareLayer

basil/HL/sram_fifo.py

@@ -12,6 +12,8 @@
 
 from basil.HL.RegisterHardwareLayer import RegisterHardwareLayer
 
+logger = logging.getLogger(__name__)
+
 
 class sram_fifo(RegisterHardwareLayer):
     '''SRAM FIFO controller interface for sram_fifo FPGA module.
@@ -46,7 +48,7 @@ def get_fifo_size(self):
         fifo_size : int
             FIFO size in units of bytes (8 bit).
         '''
-        logging.warning("Deprecated: Use get_FIFO_SIZE()")
+        logger.warning("Deprecated: Use get_FIFO_SIZE()")
         return self.FIFO_SIZE
 
     @property
@@ -70,7 +72,7 @@ def get_fifo_int_size(self):
         fifo_size : int
             FIFO size in units of integers (32 bit).
         '''
-        logging.warning("Deprecated: Use get_FIFO_INT_SIZE()")
+        logger.warning("Deprecated: Use get_FIFO_INT_SIZE()")
         return self.FIFO_INT_SIZE
 
     def get_FIFO_INT_SIZE(self):
@@ -91,7 +93,7 @@ def get_read_error_counter(self):
         fifo_size : int
             Read error counter (read attempts when SRAM is empty).
         '''
-        logging.warning("Deprecated: Use get_READ_ERROR_COUNTER()")
+        logger.warning("Deprecated: Use get_READ_ERROR_COUNTER()")
         return self.READ_ERROR_COUNTER
 
     def get_data(self):
@@ -106,13 +108,13 @@ def get_data(self):
         fifo_int_size_2 = self.FIFO_INT_SIZE
         if fifo_int_size_1 > fifo_int_size_2:
             fifo_int_size = fifo_int_size_2  # use smaller chunk
-            logging.warning("Reading wrong FIFO size. Expected: %d <= %d" % (fifo_int_size_1, fifo_int_size_2))
+            logger.warning("Reading wrong FIFO size. Expected: %d <= %d" % (fifo_int_size_1, fifo_int_size_2))
         else:
             fifo_int_size = fifo_int_size_1  # use smaller chunk
         return np.frombuffer(self._intf.read(self._conf['base_data_addr'], size=4 * fifo_int_size), dtype=np.dtype('<u4'))  # size in number of bytes
 
     def get_size(self):
         ''' *Deprecated*
         '''
-        logging.warning("Deprecated: Use get_FIFO_SIZE()")
+        logger.warning("Deprecated: Use get_FIFO_SIZE()")
         return self.FIFO_SIZE

basil/TL/Dummy.py

@@ -10,6 +10,8 @@
 
 from basil.TL.SiTransferLayer import SiTransferLayer
 
+logger = logging.getLogger(__name__)
+
 
 class Dummy(SiTransferLayer):
     '''Dummy device
@@ -21,7 +23,7 @@ def __init__(self, conf):
 
     def init(self):
         super(Dummy, self).init()
-        logging.debug(
+        logger.debug(
             "Dummy SiTransferLayer.init configuration: %s" % str(self._conf))
         if 'mem' in self._init:
             if isinstance(self._init['mem'], dict):
@@ -45,7 +47,7 @@ def write(self, addr, data):
         -------
         nothing
         '''
-        logging.debug(
+        logger.debug(
             "Dummy SiTransferLayer.write addr: %s data: %s" % (hex(addr), data))
         for curr_addr, d in enumerate(data, start=addr):
             self.mem[curr_addr] = array.array('B', [d])[0]  # write int
@@ -64,6 +66,6 @@ def read(self, addr, size):
         array : array
             Data (byte array) read from memory. Returns 0 for each byte if it hasn't been written to.
         '''
-        logging.debug("Dummy SiTransferLayer.read addr: %s size: %s" %
+        logger.debug("Dummy SiTransferLayer.read addr: %s size: %s" %
                       (hex(addr), size))
         return array.array('B', [self.mem[curr_addr] if curr_addr in self.mem else 0 for curr_addr in range(addr, addr + size)])

basil/TL/Serial.py

@@ -10,6 +10,8 @@
 
 from basil.TL.TransferLayer import TransferLayer
 
+logger = logging.getLogger(__name__)
+
 
 class Serial(TransferLayer):
     '''Transfer layer of serial device using the pySerial module.
@@ -48,7 +50,7 @@ def read(self, size=None):
 
     def query(self, data):
         if self._port.inWaiting():
-            logging.warning("Found %d bytes in the input buffer of interface %s which will be flushed" % (self._port.inWaiting(), self.name))
+            logger.warning("Found %d bytes in the input buffer of interface %s which will be flushed" % (self._port.inWaiting(), self.name))
             self._port.flushInput()
         self.write(data)
         return self._readline()

basil/TL/SiSim.py

@@ -16,6 +16,8 @@
 from basil.TL.SiTransferLayer import SiTransferLayer
 from basil.utils.sim.Protocol import WriteRequest, ReadRequest, ReadResponse, PickleInterface
 
+logger = logging.getLogger(__name__)
+
 
 class SiSim(SiTransferLayer):
 
@@ -41,7 +43,7 @@ def init(self):
             try_cnt = self._init['timeout']
 
         while(self._sock.connect_ex((host, port)) != 0):
-            logging.debug("Trying to connect to simulator.")
+            logger.debug("Trying to connect to simulator.")
             time.sleep(1)
             try_cnt -= 1
             if(try_cnt < 1):

basil/TL/SiTcp.py

@@ -19,6 +19,8 @@
 
 from basil.TL.SiTransferLayer import SiTransferLayer
 
+logger = logging.getLogger(__name__)
+
 
 class SiTcp(SiTransferLayer):
     '''SiTcp transport layer.
@@ -113,7 +115,7 @@ def chunks(array, max_len):
         elif addr == self.BASE_FAKE_FIFO_TCP:
             self.reset_fifo()
         else:
-            logging.warning("SiTcp:write - Invalid address %s" % hex(addr))
+            logger.warning("SiTcp:write - Invalid address %s" % hex(addr))
 
     def _read_single(self, addr, size):
         request = array('B', struct.pack('>BBBBI', self.RBCP_VER, self.RBCP_CMD_RD, self.RBCP_ID, size, addr))
@@ -158,7 +160,7 @@ def read(self, addr, size):
                 return array('B', struct.pack('I', self._get_tcp_data_size()))
             else:
                 return array('B', '\x00' * size)  # FIXME: workaround for SRAM module registers
-#                 logging.warning("SiTcp:read - Invalid address %s" % hex(addr))
+#                 logger.warning("SiTcp:read - Invalid address %s" % hex(addr))
 
     def _tcp_readout(self):
         while True: