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Update and improve seq_rec and seq_gen modules
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@themperek
themperek committed Jun 17, 2021
1 parent 89ab7bb commit 45e3552
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Showing 21 changed files with 304 additions and 453 deletions.
20 changes: 10 additions & 10 deletions basil/HL/seq_gen.py
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Original file line number Diff line number Diff line change
Expand Up @@ -18,20 +18,20 @@ class seq_gen(RegisterHardwareLayer):
'START': {'descr': {'addr': 1, 'size': 8, 'properties': ['writeonly']}},
'EN_EXT_START': {'descr': {'addr': 2, 'size': 1}},
'CLK_DIV': {'descr': {'addr': 3, 'size': 8}},
'SIZE': {'descr': {'addr': 4, 'size': 16}},
'WAIT': {'descr': {'addr': 6, 'size': 16}},
'REPEAT': {'descr': {'addr': 8, 'size': 16}},
'REPEAT_START': {'descr': {'addr': 10, 'size': 16}},
'NESTED_START': {'descr': {'addr': 12, 'size': 16}},
'NESTED_STOP': {'descr': {'addr': 14, 'size': 16}},
'NESTED_REPEAT': {'descr': {'addr': 16, 'size': 16}},
'MEM_BYTES': {'descr': {'addr': 18, 'size': 16, 'properties': ['ro']}},
'SIZE': {'descr': {'addr': 4, 'size': 32}},
'WAIT': {'descr': {'addr': 8, 'size': 32}},
'REPEAT': {'descr': {'addr': 12, 'size': 32}},
'REPEAT_START': {'descr': {'addr': 16, 'size': 32}},
'NESTED_START': {'descr': {'addr': 20, 'size': 32}},
'NESTED_STOP': {'descr': {'addr': 24, 'size': 32}},
'NESTED_REPEAT': {'descr': {'addr': 28, 'size': 32}},
'MEM_BYTES': {'descr': {'addr': 32, 'size': 32, 'properties': ['ro']}},
}
_require_version = "==2"
_require_version = "==3"

def __init__(self, intf, conf):
super(seq_gen, self).__init__(intf, conf)
self._seq_mem_offset = 32 # in bytes
self._seq_mem_offset = 64 # in bytes

def init(self):
super(seq_gen, self).init()
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19 changes: 12 additions & 7 deletions basil/HL/seq_rec.py
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Original file line number Diff line number Diff line change
Expand Up @@ -17,16 +17,18 @@ class seq_rec(RegisterHardwareLayer):
'READY': {'descr': {'addr': 1, 'size': 1, 'properties': ['ro']}},
'START': {'descr': {'addr': 1, 'size': 8, 'properties': ['writeonly']}},
'EN_EXT_START': {'descr': {'addr': 2, 'size': 8}},
'SIZE': {'descr': {'addr': 3, 'size': 16}}}
_require_version = "==0"
'SIZE': {'descr': {'addr': 4, 'size': 32}},
'MEM_BYTES': {'descr': {'addr': 8, 'size': 32, 'properties': ['ro']}},
}
_require_version = "==1"

def __init__(self, intf, conf):
super(seq_rec, self).__init__(intf, conf)
self._seq_mem_offset = 16 # in bytes
try:
self._seq_mem_size = conf['mem_size'] # in bytes
except KeyError:
self._seq_mem_size = 2 * 1024 # default is 2048 bytes, user should be aware of address ranges in FPGA

def init(self):
super(seq_rec, self).init()
self._seq_mem_size = self.get_mem_size()

def reset(self):
self.RESET = 0
Expand All @@ -49,6 +51,9 @@ def set_en_ext_start(self, value):
def get_en_ext_start(self):
return self.EN_EXT_START

def get_mem_size(self):
return self.MEM_BYTES

def is_done(self):
return self.is_ready

Expand All @@ -61,7 +66,7 @@ def get_done(self):

def get_data(self, size=None, addr=0):
if size and self._seq_mem_size < size:
raise ValueError('Size is too big')
raise ValueError('Size is too big memory=%d requested_size=%d' % (self._seq_mem_size, size))
if not size:
return self._intf.read(self._conf['base_addr'] + self._seq_mem_offset + addr, self._seq_mem_size)
else:
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22 changes: 12 additions & 10 deletions basil/firmware/modules/seq_gen/README.rst
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Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,9 @@ Parameters
+--------------+---------------------+-------------------------------------------------------------------------+
| Name | Default | Description |
+==============+=====================+=========================================================================+
| MEM_BYTES | 2 | Amount of memory allocated for data (in bytes) |
| MEM_BYTES | 16384 | Amount of memory allocated for data (in bytes) |
+--------------+---------------------+-------------------------------------------------------------------------+
| OUT_BITS | 2 | Size (bit) for output pattern - word size |
| OUT_BITS | 8 | Size (bit) for output pattern - word size |
+--------------+---------------------+-------------------------------------------------------------------------+

Pins
Expand All @@ -42,20 +42,22 @@ Registers
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+
| CLK_DIV | 3 | [7:0] | r/w | 1 | internal division factor for SEQ_CLK |
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+
| COUNT | 6 - 5 | [15:0] | r/w | MEM_BYTES | set the size of sequence (in words) |
| COUNT | 7 - 4 | [31:0] | r/w | out_words | set the size of sequence (in output words) |
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+
| WAIT | 7 - 6 | [15:0] | r/w | 0 | waits after every sequnce if REPEAT != 0 repeat transfer count (0 -> forever) |
| WAIT | 11 - 8 | [31:0] | r/w | 0 | waits after every sequnce if REPEAT != 0 repeat transfer count (0 -> forever) |
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+
| REPEAT | 9 - 8 | [15:0] | r/w | 0 | repeat sequence count (0 -> forever) |
| REPEAT | 15 - 12 | [31:0] | r/w | 1 | repeat sequence count (0 -> forever) |
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+
| REP_START | 11 - 10 | [15:0] | r/w | 0 | position from witch pattern will start in repeat mode (a first sequence always start at 0) |
| REP_START | 19 - 16 | [31:0] | r/w | 0 | position from witch pattern will start in repeat mode (a first sequence always start at 0) |
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+
| NESTED_START | 13 - 12 | [15:0] | r/w | 0 | position from witch pattern will start for nested loop |
| NESTED_START | 23 - 20 | [31:0] | r/w | 0 | position from witch pattern will start for nested loop |
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+
| NESTED_STOP | 15 - 14 | [15:0] | r/w | 0 | position to witch pattern will stop for nested loop |
| NESTED_STOP | 27 - 24 | [31:0] | r/w | 0 | position to witch pattern will stop for nested loop |
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+
| NESTED_REPEAT | 17 - 16 | [15:0] | r/w | 0 | repeat count for nested loop |
| NESTED_REPEAT | 31 - 28 | [31:0] | r/w | 0 | repeat count for nested loop |
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+
| DATA | 32 to 32+MEM_BYTES-1 | | r/w | unknown | memory for pattern |
| MEM_BYTES | 35 - 32 | [31:0] | r/w | MEM_BYTE | memory size |
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+
| DATA | 64 to 64+MEM_BYTES-1 | | r/w | unknown | memory for pattern |
+---------------+----------------------------------+--------+-------+-------------+--------------------------------------------------------------------------------------------+

2 changes: 1 addition & 1 deletion basil/firmware/modules/seq_gen/seq_gen.v
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ module seq_gen #(
parameter ABUSWIDTH = 16,

parameter MEM_BYTES = 16384,
parameter OUT_BITS = 16
parameter OUT_BITS = 8
) (
input wire BUS_CLK,
input wire BUS_RST,
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162 changes: 0 additions & 162 deletions basil/firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v
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46 changes: 0 additions & 46 deletions basil/firmware/modules/seq_gen/seq_gen_blk_mem_4x4096.v
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