Version 1.1 Release

Merge branch 'Docs/Rev1.1'

* Docs/Rev1.1:
  Update PLIC to Privileged Spec 1.10 Compliance
  Correct width of ID register

.gitignore

@@ -1,15 +1,2 @@
-
-docs/test.md
-*.tpbuild
-docs/.texpadtmp
-*.tdo
-*.gz
-*.out
-*.log
-*.aux
-*.toc
-*.txss
-*.toc
-*.bbl
-*.blg
 docs/build
+

DATASHEET.md

@@ -17,7 +17,7 @@ Author: Roa Logic
 
 ## Product Brief
 
-The Roa Logic AHB-Lite PLIC (Platform Level Interrupt Controller) IP is a fully parameterised soft IP implementing the Interrupt Controller defined in the *[RISC-V Privileged v1.9.1 specification](https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.9.1.pdf)*[1].
+The Roa Logic AHB-Lite PLIC (Platform Level Interrupt Controller) IP is a fully parameterised soft IP implementing the Interrupt Controller defined in the *[RISC-V Privileged v1.10 specification](https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.10.pdf)*[1].
 
 The IP features an AHB-Lite Slave interface, fully compliant with the *[AMBA 3 AHB-Lite v1.0](https://www.arm.com/products/system-ip/amba-specifications)* specifications.
 
@@ -45,7 +45,7 @@ The AHB-Lite PLIC IP core is a fully parameterised Platform-Level Interrupt Cont
 
 The purpose of the PLIC core is to connect multiple interrupt sources to one or more interrupt targets. The core supports a programmable number of simultaneous pending interrupt requests per source and individual routing of those interrupt requests to each target.
 
-Per the [RISC-V Privileged Architecture Instruction Set specification (v1.9.1)](https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.9.1.pdf), the core performs full interrupt prioritisation of each interrupt source; each may be assigned a separate priority and enabled per target via a matrix of interrupt enable bits. Further, an optional priority threshold per target may be defined to mask lower priority interrupts.
+Per the [RISC-V Privileged Architecture Instruction Set specification (v1.10)](https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.10.pdf), the core performs full interrupt prioritisation of each interrupt source; each may be assigned a separate priority and enabled per target via a matrix of interrupt enable bits. Further, an optional priority threshold per target may be defined to mask lower priority interrupts.
 
 To reduce latency, the PLIC core presents all asserted interrupts to the target in priority order, queuing them so that a software interrupt handler can service all pending interrupts without the need to restore the interrupted context.
 
@@ -55,7 +55,7 @@ For illustration, a simplified example system using the PLIC core is shown below
 
 ### PLIC Operation
 
-As stated in the [RISC-V Privileged Architecture Instruction Set specification (v1.9.1)](https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.9.1.pdf):
+As stated in the [RISC-V Privileged Architecture Instruction Set specification (v1.10)](https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.10.pdf):
 
 > PLIC connects global *interrupt sources*, which are usually I/O devices, to *interrupt targets*, which are usually *hart contexts*. The PLIC contains multiple *interrupt gateways*, one per interrupt source, together with a *PLIC core* that performs interrupt prioritization and routing. Global interrupts are sent from their source to an *interrupt gateway* that processes the interrupt signal from each source and sends a single *interrupt request* to the PLIC core, which latches these in the core interrupt pending bits (IP). Each interrupt source is assigned a separate priority. The PLIC core contains a matrix of interrupt enable (IE) bits to select the interrupts that are enabled for each target. The PLIC core forwards an *interrupt notification* to one or more targets if the targets have any pending interrupts enabled, and the priority of the pending interrupts exceeds a per-target threshold. When the target takes the external interrupt, it sends an *interrupt claim* request to retrieve the identifier of the highest-priority global interrupt source pending for that target from the PLIC core, which then clears the corresponding interrupt source pending bit. After the target has serviced the interrupt, it sends the associated interrupt gateway an *interrupt completion* message and the interrupt gateway can now forward another interrupt request for the same source to the PLIC.
 
@@ -318,7 +318,7 @@ The operation and run-time configuration of the PLIC is managed via a memory map
 |   `CONFIG`   |       1       |               64               |    RO    | Configuration                                                 |
 |     `EL`     |       1       |            `SOURCES`           |    RW    | Edge/Level Trigger                                            |
 |     `IE`     |   `TARGETS`   |            `SOURCES`           |    RW    | Interrupt Enable                                              |
-|     `ID`     |   `TARGETS`   |   clog<sub>2</sub>(`SOURCES`)  |    RW    | ID of Highest priority IRQ, Int. Claim (R), Int. Complete (W) |
+|     `ID`     |   `TARGETS`   |  clog<sub>2</sub>(`SOURCES+1`) |    RW    | ID of Highest priority IRQ, Int. Claim (R), Int. Complete (W) |
 |  `PRIORITY`  |   `SOURCES`   | clog<sub>2</sub>(`PRIORITIES`) |    RW    | Priority Level                                                |
 |  `THRESHOLD` |   `TARGETS`   | clog<sub>2</sub>(`PRIORITIES`) |    RW    | Priority Threshold                                            |
 
@@ -387,6 +387,8 @@ When a target reads this register, this also indicates the target has claimed th
 
 A target then writes to this register to indicate completion of servicing the interrupt source. It is the action of writing to this register which generates the interrupt completion notification – the value written will be ignored. Instead the register continues to identify the highest priority interrupt source to be serviced.
 
+Given an ID of zero means that no interrupt is pending, the width of this register must be sufficient to support `SOURCES` number of interrupt sources. This means the width of ID register = clog<sub>2</sub>(`SOURCES+1`)
+
 ##### PRIORITY\[\]
 
 The `PRIORITY[]` Read/Write registers define the priority level of each interrupt source. Interrupt priority increases with larger values of `PRIORITY`.
@@ -673,15 +675,15 @@ The PLIC is designed to be compliant with the following specifications, as licen
 
 > “The [RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 2.2](https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-spec-v2.2.pdf)", Editors Andrew Waterman and Krste Asanović,RISC-V Foundation, May 2017.
 
-> “The [RISC-VInstruction Set Manual, Volume II: Privileged Architecture, Version 1.9.1](https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.9.1.pdf)",Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, November 2016
+> “The [RISC-VInstruction Set Manual, Volume II: Privileged Architecture, Version 1.10](https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.10.pdf)", Editors Andrew Waterman and Krste Asanović, RISC-V Foundation, May 2017.
 
 ## Revision History
 
-|   **Date**  | **Rev.** | **Comments**    |
-|:-----------:|:--------:|:----------------|
-| 13-Oct-2017 |    1.0   | Initial Release |
-|             |          |                 |
-|             |          |                 |
-|             |          |                 |
+|   **Date**  | **Rev.** | **Comments**                            |
+|:-----------:|:--------:|:----------------------------------------|
+| 13-Oct-2017 |    1.0   | Initial Release                         |
+| 01-Dec-2017 |    1.1   | RISC-V Privileged Spec v1.10 compliance |
+|             |          |                                         |
+|             |          |                                         |
 
 [1] Full specification details are provided in the References section

docs/AHB-Lite_PLIC_Datasheet.tex

@@ -1,4 +1,4 @@
-\documentclass[twoside,11pt,openany]{book}
+\documentclass[a4paper,oneside,11pt,openany]{book}
 
 % Document Setup
 \input{tex/preamble.tex}

docs/pkg/roalogictitle.sty

@@ -20,29 +20,47 @@
 \newcommand*{\header}[1]{\gdef\@header{#1}%
 }
 
+\newcommand*{\version}[1]{\gdef\@version{#1}%
+}
+
+\newcommand*{\heading}[1]{\gdef\@heading{#1}%
+}
+
+\appendiargdef{\version}{%
+\begingroup
+\renewcommand{\thanks}[1]{}
+\protected@xdef\theversion{#1}
+\endgroup}
+
+\appendiargdef{\heading}{%
+\begingroup
+\renewcommand{\thanks}[1]{}
+\protected@xdef\theheading{#1}
+\endgroup}
+
 % Overload \maketitle with new layout
 \renewcommand*{\maketitle}{%
 \hypersetup{pageanchor=false}
 \begin{titlepage}
 \par
 \vspace{3cm}
 {\raggedleft%
-	\includegraphics[width=12cm]{assets/img/Tagged_Logo}\par
+	\includegraphics[width=12cm]{assets/img/Tagged_Logo.eps}\par
 }\vspace{1cm}
 	\centering
 {\huge\bfseries\@title\unskip\strut\par}
 \vspace{1cm}
-{\LARGE\itshape\@doctype\unskip\strut\par}
+{\LARGE\itshape\@doctype\space(v\@version)\unskip\strut\par}
 \vspace{1cm}
 {\scshape\Large\@project\unskip\strut\par}
 \vspace{1cm}
 {\large \@date\par}
 \vspace{7cm}
-{\scshape\large (c) Roa Logic B.V. \par}
+{\scshape\large \copyright\space Roa Logic B.V. \par}
 
 \vfill
 
 \end{titlepage}
 \hypersetup{pageanchor=true}
 }
-\endinput
+\endinput

docs/tex/history.tex

@@ -9,9 +9,9 @@ \chapter{Revision History}
 	\midrule
 	\endhead
 		13-Oct-2017 & 1.0 & Initial Release\\
-		              &     & \\
-		              &     & \\
-		              &     & \\
+		01-Dec-2017 & 1.1 & RISC-V Privileged Spec v1.10 compliance\\
+		            &     & \\
+		            &     & \\
 	\bottomrule
 	\caption{Revision History}
 	\label{tab:REVS}

docs/tex/interfaces.tex

@@ -237,7 +237,7 @@ \section{Register Interface}
 	\texttt{CONFIG}    & 1 & 64 & RO & Configuration\\
 	\texttt{EL}        & 1 & \texttt{SOURCES} & RW & Edge/Level Trigger\\
 	\texttt{IE}        & \texttt{TARGETS} & \texttt{SOURCES} & RW & Interrupt Enable\\
-	\texttt{ID}        & \texttt{TARGETS} & clog\textsubscript{2}(\texttt{SOURCES}) & RW & ID of Highest priority IRQ, \newline Int. Claim (R), \newline Int. Complete (W)\\
+	\texttt{ID}        & \texttt{TARGETS} & clog\textsubscript{2}(\texttt{SOURCES+1})  & RW & ID of Highest priority IRQ, \newline Int. Claim (R), \newline Int. Complete (W)\\
 	\texttt{PRIORITY}  & \texttt{SOURCES} & clog\textsubscript{2}(\texttt{PRIORITIES}) & RW & Priority Level\\
 	\texttt{THRESHOLD} & \texttt{TARGETS} & clog\textsubscript{2}(\texttt{PRIORITIES}) & RW & Priority Threshold \\
 	\bottomrule
@@ -367,6 +367,10 @@ \subsubsection{ID[]}
 It is the action of writing to this register which generates the interrupt completion notification -- the
 value written will be ignored. Instead the register continues to identify the highest priority interrupt source to be serviced.
 
+Given an ID of zero means that no interrupt is pending, the width of this register must be sufficient to support \texttt{SOURCES} number of interrupt sources. This means the width of ID register = clog\textsubscript{2}(\texttt{SOURCES+1})
+
+
+
 \subsubsection{PRIORITY[]}
 
 The \texttt{PRIORITY[]} Read/Write registers define the priority level of each interrupt source. Interrupt priority increases with larger values of \texttt{PRIORITY}.

docs/tex/introduction.tex

@@ -1,6 +1,6 @@
 \chapter{Product Brief}
 
-The Roa Logic AHB-Lite PLIC (Platform Level Interrupt Controller) IP is a fully parameterised soft IP implementing the Interrupt Controller defined in the \emph{\href{https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.9.1.pdf}{RISC-V Privileged v1.9.1 specification}}\footnote{Full specification details are provided in the References section}.
+The Roa Logic AHB-Lite PLIC (Platform Level Interrupt Controller) IP is a fully parameterised soft IP implementing the Interrupt Controller defined in the \emph{\href{https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.10.pdf}{RISC-V Privileged v1.10 specification}}\footnote{Full specification details are provided in the References section}.
 
 The IP features an AHB-Lite Slave interface, fully compliant with the \emph{\href{https://www.arm.com/products/system-ip/amba-specifications}{AMBA 3 AHB-Lite v1.0}} specifications.
 

docs/tex/preamble.tex

@@ -56,7 +56,6 @@
 \urlstyle{same}
 
 % Font & Colour control
-
 \renewcommand{\familydefault}{\rmdefault}
 \renewcommand{\headlinecolor}{\color{rlcolor}}
 

docs/tex/references.tex

@@ -9,7 +9,7 @@ \chapter{References}
 \end{quote}
 
 \begin{quote}
-	``The \href{https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.9.1.pdf}{RISC-VInstruction Set Manual, Volume II: Privileged Architecture,
-	Version 1.9.1}",Editors Andrew Waterman and Krste Asanović, RISC-V
-	Foundation, November 2016
+	``The \href{https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.10.pdf}{RISC-VInstruction Set Manual, Volume II: Privileged Architecture,
+	Version 1.10}", Editors Andrew Waterman and Krste Asanović, RISC-V
+	Foundation, May 2017.
 \end{quote}

docs/tex/setup.tex

@@ -1,22 +1,25 @@
 % Load Roalogic Title Page Generator
 \usepackage{pkg/roalogictitle}
 
+\graphicspath{ {./assets/img/} }
+
 % Document Variables
 
 \title{AHB-Lite Platform Level Interrupt Controller}
-\header{AHB-Lite Platform Level Interrupt Controller}
+\heading{AHB-Lite Platform Level Interrupt Controller}
 \author{Roa Logic}
-\date{1st October, 2017}
+\date{1st December, 2017}
+\version{1.1}
 \doctype{Datasheet}
 \project{http://roalogic.github.io/plic}
 \author{Paul Hardy}
 
  % Set page headers/footer
 \pagestyle{fancy}
 \fancyhf{}
-\fancyhead[LE,RO]{AHB-Lite Platform Level Interrupt Controller}
-\fancyhead[RE,LO]{Roa Logic}
-\fancyfoot[CE,CO]{\thepage}
+\fancyhead[L]{\theheading\space(v\theversion)}
+\fancyhead[R]{\includegraphics[width=50px,trim=0 25px 0 0]{assets/img/RoaLogicHeader}}
+\fancyfoot[C]{\thepage}
 % \fancyhead[R]{\thepage}
 % \fancyhead[L]{AHB-Lite Platform Level Interrupt Controller}
 % \fancyfoot[C]{\textcircled{c} Roa Logic}

docs/tex/specification.tex

@@ -9,7 +9,7 @@ \section{Overview}
 one or more interrupt targets. The core supports a programmable number
 of simultaneous pending interrupt requests per source and individual routing of those interrupt requests to each target.
 
-Per the \href{https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.9.1.pdf}{RISC-V Privileged Architecture Instruction Set specification (v1.9.1)}, the core performs full interrupt prioritisation of each interrupt source; each may be assigned a separate priority and enabled per target via a matrix of interrupt enable bits. Further, an optional priority threshold per target may be defined to mask lower priority interrupts.
+Per the \href{https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.10.pdf}{RISC-V Privileged Architecture Instruction Set specification (v1.10)}, the core performs full interrupt prioritisation of each interrupt source; each may be assigned a separate priority and enabled per target via a matrix of interrupt enable bits. Further, an optional priority threshold per target may be defined to mask lower priority interrupts.
 
 To reduce latency, the PLIC core presents all asserted interrupts to the target in priority order, queuing them so that a software interrupt handler can service all pending interrupts without the need to restore the interrupted context.
 
@@ -23,7 +23,7 @@ \section{Overview}
 
 \section{PLIC Operation}
 
-As stated in the \href{https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.9.1.pdf}{RISC-V Privileged Architecture Instruction Set specification (v1.9.1)}:
+As stated in the \href{https://github.com/riscv/riscv-isa-manual/blob/master/release/riscv-privileged-v1.10.pdf}{RISC-V Privileged Architecture Instruction Set specification (v1.10)}:
 
 \begin{quote}