Correct width of ID register

- Width should be clog2(SOURCES+1) to accommodate ID=0 → No IRQ Pending

.gitignore

@@ -1,15 +1,2 @@
-
-docs/test.md
-*.tpbuild
-docs/.texpadtmp
-*.tdo
-*.gz
-*.out
-*.log
-*.aux
-*.toc
-*.txss
-*.toc
-*.bbl
-*.blg
 docs/build
+

docs/tex/interfaces.tex

@@ -237,7 +237,7 @@ \section{Register Interface}
 	\texttt{CONFIG}    & 1 & 64 & RO & Configuration\\
 	\texttt{EL}        & 1 & \texttt{SOURCES} & RW & Edge/Level Trigger\\
 	\texttt{IE}        & \texttt{TARGETS} & \texttt{SOURCES} & RW & Interrupt Enable\\
-	\texttt{ID}        & \texttt{TARGETS} & clog\textsubscript{2}(\texttt{SOURCES}) & RW & ID of Highest priority IRQ, \newline Int. Claim (R), \newline Int. Complete (W)\\
+	\texttt{ID}        & \texttt{TARGETS} & clog\textsubscript{2}(\texttt{SOURCES+1})  & RW & ID of Highest priority IRQ, \newline Int. Claim (R), \newline Int. Complete (W)\\
 	\texttt{PRIORITY}  & \texttt{SOURCES} & clog\textsubscript{2}(\texttt{PRIORITIES}) & RW & Priority Level\\
 	\texttt{THRESHOLD} & \texttt{TARGETS} & clog\textsubscript{2}(\texttt{PRIORITIES}) & RW & Priority Threshold \\
 	\bottomrule
@@ -367,6 +367,10 @@ \subsubsection{ID[]}
 It is the action of writing to this register which generates the interrupt completion notification -- the
 value written will be ignored. Instead the register continues to identify the highest priority interrupt source to be serviced.
 
+Given an ID of zero means that no interrupt is pending, the width of this register must be sufficient to support \texttt{SOURCES} number of interrupt sources. This means the width of ID register = clog\textsubscript{2}(\texttt{SOURCES+1})
+
+
+
 \subsubsection{PRIORITY[]}
 
 The \texttt{PRIORITY[]} Read/Write registers define the priority level of each interrupt source. Interrupt priority increases with larger values of \texttt{PRIORITY}.