RISC-V BASED CPU DESIGN

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This repository is the outcome of RISC-V MYTH (Microprocessor for You in Thirty Hours) workshop conducted by VSDFLOW and REDWOOD-EDA. It contains all the information needed to build your RISC-V pipelined core, which has support of base interger RV32I instruction format using TL-Verilog on makerchip platform.

TABLE OF CONTENTS

1. Introduction to RISC-V ISA

2. GNU Compiler Toolchain

3. Introduction to ABI

4. Digital Logic with TL-Verilog and Makerchip

   4.1 Playing with Makerchip

   4.2 Calculator - Combinational Logic

   4.3 Calculator - sequential Logic

   4.4 Pipeline in Calculator

   4.5 Validity in calculator

5. Basic RISC-V CPU micro-architecture

6. Acknowledgements

1. Introduction to RISC-V ISA

ISA (Instruction Set Architecture ) defines the set of basic operations defines how the CPU is controlled by software. It is an interface between hardware and software.

RISC-V is an ISA developed with RISC (Reduced Instruction Set Computer) principle. It is revolutionary because of it's open source nature and it has smaller set of instruction compared to CISC(Complex Instruction Set Computer).

More details on RISC-V ISA can be obtained here

2. GNU Compiler Toolchain

The GNU Toolchain is a set of programming tools in Linux systems that programmers can use to make and compile their code to produce a program or library. Following is the list of command used to debug the program:

To use the risc-v gcc compiler use the below command:

riscv64-unknown-elf-gcc -Ofast -mabi=lp64 -march=rv64i -o <object filename> <C filename>

More generic command with different options:

riscv64-unknown-elf-gcc <compiler option -O1 ; Ofast> <ABI specifier -lp64; -lp32; -ilp32> <architecture specifier -RV64 ; RV32> -o <object filename> <C filename>

More details on compiler options can be obtained here

To view assembly code use the below command,

riscv64-unknown-elf-objdump -d <object filename>

Below is the output of object dump captured when debugging the printf address.

To use SPIKE simualtor to run risc-v obj file use the below command,

spike pk <object filename>

To use SPIKE as debugger

spike -d pk <object Filename> with degub command as until pc 0 <pc of your choice>

To view the registers we can use command as

reg <core> <register name>.

3. Introduction to ABI

In computer software, an application binary interface (ABI) is an interface between two binary program modules. Often, one of these modules is a library or operating system facility, and the other is a program that is being run by a user.Words from wiki ABI is also called as system call interface used by the application program to access the registers specific to architecture. Since the MYTH workshop is using RISC-V architecture, it is good to know the register details in detail.

There are around 32 registers in RISCV ISA, since only 5-bits are alloted for registers. Other than x0 (which is hardwired to zero) remaining registers are good to use.

4. Digital Logic with TL-Verilog and Makerchip

Makerchip is a free online environment for developing high-quality integrated circuits. You can code, compile, simulate, and debug Verilog designs, all from your browser. Your code, block diagrams, and waveforms are tightly integrated.

All the examples shown below are done on Makerchip IDE using TL-verilog. Also there are other tutorials present on IDE which can be found here under Tutorials section.

4.1 Playing with Makerchip

Before start playing the game (Designing a RISC-V CPU) it is good to know/familiarize with the ground (IDE). So we were tasked to design some basic logic gates using TL-Verilog and explore the options/features in the makerchip platform.
Designed gates such as Inverted, Operations on gates, vector ,counter and Mux.

Inverter

Operations on gates

Vector

MUX

MUX with Vector

Free running counter

4.2 Calculator - Combinational Logic

So the real learning started by designing a calculator. Beauty of the makerchip is there is no need for declaration for the variable used in the program unlike verilog. There is also no need to create testbench for simple logic such as calculator, makerchip provides random stimulus to the inputs. As you can observe the random values in the wavefor (bottom right corner).

Below is the snapshot of calculator with combinational logic.

4.3 Calculator - sequential Logic

To get started on the sequential logic, before implementing in calculator we implemented in fibonacci series as below:

Interesting thing about one of the operators used above ">>n" is ahead operator. which will provide the value of that signal n cycle before. Coming back to sequential calculator, used the above mentioned ahead operator to calculate the previous output in as input (Line 16)

4.4 Pipelined logic

Timing abstract powerful feature of TL-Verilog which converts a code into pipeline stages easily. Whole code under |pipe scope with stages defined as @?

Below is snapshot of 2-cycle calculator which clears the output alternatively and output of given inputs are observed at the next cycle.

4.5 Validity

?valid 

This validty executes the block (whithin their scope) when it is true. This operator provides easier debug, cleaner design, better error checking, automated clock gating. Below is 2-cycle with validity

5. Basic RISC-V CPU micro-architecture

Designing the basic processor of 3 stages Fetch -> Decode -> Execute based on RISC-V ISA. If a processor is mentioned as single cycle processor then it is capable of executing Fetch -> Decode -> Execute all instruction in a single cycle.

Fetch

Program Counter (PC): Holds the address of next Instruction
Instruction Memory (IM): Holds the set of instructions to be executed

During fetch stage, processor fetch instruction from IM directed by PC.

Decode

In this stage, the instruction fetched from the previous stage is dismantled in decode stage. It will decode into opcode, immediate value, source address and destination address. decode happens based on the instruction format and types of instruction.

Execute

In this stage, based on the opcode, respectice operation is performed on the sorce and destination register. Initally we implemented ADD and ADDI to make the sum of 1 to n C program running on the top of the RSIC V cpu that we are developing.

After implementing the Branch, control logic and after some debugging got the expected output from the C program which is 45 (sum of numbers from 1 to 9).

Then we started updating the code with pipeline logic and self checking condition *passed = |cpu/xreg[15]>>5$value == (1+2+3+4+5+6+7+8+9);

Finally added the remaining Arithmetic, Branch, Load, Jump instruction we completed the RISC V CPU design.

Makechip IDE: RISC V CPU

Final Code : CPU

Acknowledgements

Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd.

Steve Hoover, Founder, Redwood EDA

Shivam Potdar, GSoC 2020 @fossi-foundation