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Core: define __PKHBT and __PKHTB when __RISCV_FEATURE_DSP=1
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Signed-off-by: Huaqi Fang <[email protected]>
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fanghuaqi committed Aug 13, 2021
1 parent 9819c71 commit 6f8cb36
Showing 1 changed file with 11 additions and 10 deletions.
21 changes: 11 additions & 10 deletions NMSIS/Core/Include/core_feature_dsp.h
Original file line number Diff line number Diff line change
Expand Up @@ -18642,20 +18642,21 @@ __STATIC_FORCEINLINE int32_t __SMMLA(int32_t op1, int32_t op2, int32_t op3)
#define __PKTT16 __RV_PKTT16
#define __KADD16 __RV_KADD16
#define __SADD16 __RV_ADD16
#define __SSUB8 __RV_KSUB8
#define __SADD8 __RV_KADD8
#define __USAT16 __RV_UCLIP16

#endif /* (__RISCV_FEATURE_DSP == 1) */
#define __SSUB8 __RV_KSUB8
#define __SADD8 __RV_KADD8
#define __USAT16 __RV_UCLIP16

/** \brief Halfword packing instruction. Combines bits[15:0] of val1 with bits[31:16] of val2 levitated with the val3. */
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
/** \brief Halfword packing instruction. Combines bits[31:16] of val1 with bits[15:0] of val2 right-shifted with the val3. */
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )

/** first rotate then extract. This is more suitable for arm compiler for it can rotate and extract in one command*/
#define __SXTB16_RORn(ARG1, ARG2) __RV_SUNPKD820(__ROR(ARG1, ARG2))
#define __SXTB16_RORn(ARG1, ARG2) __RV_SUNPKD820(__ROR(ARG1, ARG2))

#endif /* (__RISCV_FEATURE_DSP == 1) */

#endif /* defined(__DSP_PRESENT) && (__DSP_PRESENT == 1) */

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