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* adding shell v1.4 new file: shell_v04261818/build/constraints/cl_clocks_aws.xdc new file: shell_v04261818/build/constraints/cl_ddr.xdc new file: shell_v04261818/build/constraints/cl_debug_bridge.xdc new file: shell_v04261818/build/constraints/cl_synth_aws.xdc new file: shell_v04261818/build/constraints/xsdbm_timing_exception.xdc new file: shell_v04261818/build/scripts/apply_debug_constraints.tcl new file: shell_v04261818/build/scripts/aws_build_dcp_from_cl.sh new file: shell_v04261818/build/scripts/aws_clock_properties.tcl new file: shell_v04261818/build/scripts/aws_dcp_verify.tcl new file: shell_v04261818/build/scripts/aws_gen_clk_constraints.tcl new file: shell_v04261818/build/scripts/check_uram.tcl new file: shell_v04261818/build/scripts/device_type.tcl new file: shell_v04261818/build/scripts/params.tcl new file: shell_v04261818/build/scripts/prepare_build_environment.sh new file: shell_v04261818/build/scripts/step_user.tcl new file: shell_v04261818/build/scripts/strategy_BASIC.tcl new file: shell_v04261818/build/scripts/strategy_CONGESTION.tcl new file: shell_v04261818/build/scripts/strategy_DEFAULT.tcl new file: shell_v04261818/build/scripts/strategy_EXPLORE.tcl new file: shell_v04261818/build/scripts/strategy_TIMING.tcl new file: shell_v04261818/build/scripts/uram_options.tcl new file: shell_v04261818/build/scripts/vivado_keyfile.txt new file: shell_v04261818/build/scripts/vivado_keyfile_2017_4.txt new file: shell_v04261818/build/scripts/vivado_vhdl_keyfile.txt new file: shell_v04261818/build/scripts/vivado_vhdl_keyfile_2017_4.txt new file: shell_v04261818/design/interfaces/README.md new file: shell_v04261818/design/interfaces/cl_ports.vh new file: shell_v04261818/design/interfaces/unused_apppf_irq_template.inc new file: shell_v04261818/design/interfaces/unused_cl_sda_template.inc new file: shell_v04261818/design/interfaces/unused_ddr_a_b_d_template.inc new file: shell_v04261818/design/interfaces/unused_ddr_c_template.inc new file: shell_v04261818/design/interfaces/unused_dma_pcis_template.inc new file: shell_v04261818/design/interfaces/unused_flr_template.inc new file: shell_v04261818/design/interfaces/unused_pcim_template.inc new file: shell_v04261818/design/interfaces/unused_sh_bar1_template.inc new file: shell_v04261818/design/interfaces/unused_sh_ocl_template.inc new file: shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0.veo new file: shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0.vho new file: shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0.xci new file: shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0.xml new file: shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0_clocks.xdc new file: shell_v04261818/design/ip/axi_clock_converter_0/axi_clock_converter_0_ooc.xdc new file: shell_v04261818/design/ip/axi_clock_converter_0/doc/axi_clock_converter_v2_1_changelog.txt new file: shell_v04261818/design/ip/axi_clock_converter_0/hdl/axi_clock_converter_v2_1_vl_rfs.v new file: shell_v04261818/design/ip/axi_clock_converter_0/hdl/axi_infrastructure_v1_1_0.vh new file: shell_v04261818/design/ip/axi_clock_converter_0/hdl/axi_infrastructure_v1_1_vl_rfs.v new file: shell_v04261818/design/ip/axi_clock_converter_0/hdl/blk_mem_gen_v8_4_vhsyn_rfs.vhd new file: shell_v04261818/design/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.v new file: shell_v04261818/design/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_rfs.vhd new file: shell_v04261818/design/ip/axi_clock_converter_0/hdl/fifo_generator_v13_2_vhsyn_rfs.vhd new file: shell_v04261818/design/ip/axi_clock_converter_0/sim/axi_clock_converter_0.v new file: shell_v04261818/design/ip/axi_clock_converter_0/simulation/fifo_generator_vlog_beh.v new file: shell_v04261818/design/ip/axi_clock_converter_0/synth/axi_clock_converter_0.v new file: shell_v04261818/design/ip/axi_register_slice/axi_register_slice.veo new file: shell_v04261818/design/ip/axi_register_slice/axi_register_slice.vho new file: shell_v04261818/design/ip/axi_register_slice/axi_register_slice.xci new file: shell_v04261818/design/ip/axi_register_slice/axi_register_slice.xml new file: shell_v04261818/design/ip/axi_register_slice/doc/axi_register_slice_v2_1_changelog.txt new file: shell_v04261818/design/ip/axi_register_slice/hdl/axi_infrastructure_v1_1_0.vh new file: shell_v04261818/design/ip/axi_register_slice/hdl/axi_infrastructure_v1_1_vl_rfs.v new file: shell_v04261818/design/ip/axi_register_slice/hdl/axi_register_slice_v2_1_vl_rfs.v new file: shell_v04261818/design/ip/axi_register_slice/sim/axi_register_slice.v new file: shell_v04261818/design/ip/axi_register_slice/synth/axi_register_slice.v new file: shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.veo new file: shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.vho new file: shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.xci new file: shell_v04261818/design/ip/axi_register_slice_light/axi_register_slice_light.xml new file: shell_v04261818/design/ip/axi_register_slice_light/doc/axi_register_slice_v2_1_changelog.txt new file: shell_v04261818/design/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_0.vh new file: shell_v04261818/design/ip/axi_register_slice_light/hdl/axi_infrastructure_v1_1_vl_rfs.v new file: shell_v04261818/design/ip/axi_register_slice_light/hdl/axi_register_slice_v2_1_vl_rfs.v new file: shell_v04261818/design/ip/axi_register_slice_light/sim/axi_register_slice_light.v new file: shell_v04261818/design/ip/axi_register_slice_light/synth/axi_register_slice_light.v new file: shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect.bd new file: shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect.bxml new file: shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect.dcp new file: shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect_ooc.xdc new file: shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect_sim_netlist.v new file: shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect_sim_netlist.vhdl new file: shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect_stub.v new file: shell_v04261818/design/ip/cl_axi_interconnect/cl_axi_interconnect_stub.vhdl new file: shell_v04261818/design/ip/cl_axi_interconnect/hdl/cl_axi_interconnect_wrapper.v new file: shell_v04261818/design/ip/cl_axi_interconnect/hw_handoff/cl_axi_interconnect.hwh new file: shell_v04261818/design/ip/cl_axi_interconnect/hw_handoff/cl_axi_interconnect_bd.tcl new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_axi_interconnect_0_0/cl_axi_interconnect_axi_interconnect_0_0.xci new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_axi_interconnect_0_0/cl_axi_interconnect_axi_interconnect_0_0.xml new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xci new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xml new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0_ooc.xdc new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/sim/cl_axi_interconnect_m00_regslice_0.v new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m00_regslice_0/synth/cl_axi_interconnect_m00_regslice_0.v new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/cl_axi_interconnect_m01_regslice_0.xci new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/cl_axi_interconnect_m01_regslice_0.xml new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/cl_axi_interconnect_m01_regslice_0_ooc.xdc new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/sim/cl_axi_interconnect_m01_regslice_0.v new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m01_regslice_0/synth/cl_axi_interconnect_m01_regslice_0.v new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/cl_axi_interconnect_m02_regslice_0.xci new file: shell_v04261818/design/ip/cl_axi_interconnect/ip/cl_axi_interconnect_m02_regslice_0/cl_axi_interconnect_m02_regslice_0.xml new file: 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shell_v04261818/design/ip/cl_axi_interconnect/ipshared/b752/hdl/generic_baseblocks_v2_1_vl_rfs.v new file: shell_v04261818/design/ip/cl_axi_interconnect/ipshared/c631/hdl/axi_crossbar_v2_1_vl_rfs.v new file: shell_v04261818/design/ip/cl_axi_interconnect/ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh new file: shell_v04261818/design/ip/cl_axi_interconnect/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v new file: shell_v04261818/design/ip/cl_axi_interconnect/sim/cl_axi_interconnect.v new file: shell_v04261818/design/ip/cl_axi_interconnect/synth/cl_axi_interconnect.hwdef new file: shell_v04261818/design/ip/cl_axi_interconnect/synth/cl_axi_interconnect.v new file: shell_v04261818/design/ip/cl_axi_interconnect/ui/bd_26ef0651.ui new file: shell_v04261818/design/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xci new file: shell_v04261818/design/ip/cl_axi_interconnect_m00_regslice_0/cl_axi_interconnect_m00_regslice_0.xml new file: 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new file: shell_v04261818/hlx/hlx_setup.tcl new file: shell_v04261818/hlx/verif/cl_ports_sh_bfm.vh new file: shell_v04261818/hlx/verif/scripts/dpi.tcl new file: shell_v04261818/hlx/verif/scripts/dpi_xsim.tcl new file: shell_v04261818/hlx/verif/tb.sv new file: shell_v04261818/hlx/verif/test_cl.sv new file: shell_v04261818/new_cl_template/build/README.md new file: shell_v04261818/new_cl_template/build/constraints/cl_pnr_user.xdc new file: shell_v04261818/new_cl_template/build/constraints/cl_synth_user.xdc new file: shell_v04261818/new_cl_template/build/scripts/aws_build_dcp_from_cl.sh new file: shell_v04261818/new_cl_template/build/scripts/create_dcp_from_cl.tcl new file: shell_v04261818/new_cl_template/build/scripts/encrypt.tcl new file: shell_v04261818/new_cl_template/build/scripts/synth_cl_hello_world.tcl new file: shell_v04261818/new_cl_template/design/cl_template.sv new file: shell_v04261818/new_cl_template/design/cl_template_defines.vh new file: shell_v04261818/shell_version.txt * removing v1.3 shell * merging shell V1.4 updates to public * updating xilinx/SDAccel_examples to latest on aws_2017.1 branch * fixing merge issues * document updates
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