Implementation of ASPDAC 2021 paper: "Read your circuit: Leveraging word embedding to guide logic optimization"
-
Benchmarks/aspdac directory contain the designs on which synthesis, place and route can be done.
-
Each design have a folder "template" having subfolder "GENUS". The "src" folder contain the source codes.
-
"GENUS" have a config.tcl, file_list.f and a Makefile. The Makefile is linked to the common Makefile.common in scripts directory.
-
"file_list.f" contains the list of source files in the "src" folder. config.tcl have the necessary environment variables.
-
Copy the freepdk-45nm folder to your $HOME directory.
-
Run commands (inside template folder):
Synthesis: make genus Placement and rounting: make pnr_jg
-
Run the following scripts to extract timing data (location: codes/dataprocess):
Timing report and input features: python3 etGen.py -t ../../benchmarks/aspdac/picosoc/template/GENUS/out/results/picosoc_generic_timing.rpt -d [TargetCT] -o [output data dump folder]
Timing report post techmap: python3 etTech.py -t ../../benchmarks/aspdac/picosoc/template/GENUS/out/results/picosoc_techmap_timing.rpt -o [output data dump folder]
Timing report post PnR: python3 etpostPnR.py -t ../../benchmarks/aspdac/picosoc/template/GENUS/out_pnr/rpts/timing.rpt -o [output data dump folder]