Vendorize RISC-V specs at tag 2023-10-02. (openhwgroup#1963)

* vendor/riscv/riscv-isa-manual: New vendorized repo. * vendor/riscv_riscv-isa-manual.lock.hjson: Ditto. * vendor/riscv_riscv-isa-manual.vendor.hjson: Ditto.
MarioOpenHWGroup · Mar 25, 2024 · f73724b · f73724b
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diff --git a/vendor/riscv/riscv-isa-manual/.gitignore b/vendor/riscv/riscv-isa-manual/.gitignore
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+.DS_Store
+.*.swp
diff --git a/vendor/riscv/riscv-isa-manual/LICENSE b/vendor/riscv/riscv-isa-manual/LICENSE
diff --git a/vendor/riscv/riscv-isa-manual/README.md b/vendor/riscv/riscv-isa-manual/README.md
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+# RISC-V Instruction Set Manual
+
+[![RISC-V ISA Build](https://github.com/riscv/riscv-isa-manual/actions/workflows/isa-build.yml/badge.svg)](https://github.com/riscv/riscv-isa-manual/actions/workflows/isa-build.yml)
+
+This repository contains the source files for the RISC-V Instruction Set Manual, which is comprised of the Privileged RISC-V Instruction Set Manual (LaTeX) and the Unprivileged RISC-V Instruction Set Manual (AsciiDoc). The preface of each document indicates the version of each standard that has been formally ratified by RISC-V International.
+
+This work is licensed under a [Creative Commons Attribution 4.0 International License](https://creativecommons.org/licenses/by/4.0/). See the [LICENSE](LICENSE) file for details.
+
+The RISC-V Instruction Set Manual is organized into the following volumes:
+
+- Volume I: User-Level ISA
+- Volume II: Privileged Architecture
+
+## Official and Draft Versions
+
+- **Official versions** of the specifications are available at the [RISC-V International website](https://riscv.org/specifications/).
+- **Compiled versions of the most recent drafts** of the specifications can be found on the [GitHub releases page](https://github.com/riscv/riscv-isa-manual/releases/latest).
+- **Older official versions** of the specifications are archived at the [GitHub releases archive](https://github.com/riscv/riscv-isa-manual/releases/tag/archive).
+
+The canonical list of **open-source RISC-V implementations' marchid CSR values** is available in the [marchid.md file](https://github.com/riscv/riscv-isa-manual/blob/main/marchid.md).
+
+## Contributing
+
+If you would like to contribute to this documentation, please refer to the [Documentation Developer's Guide](https://github.com/riscv/docs-dev-guide).
+
+The recommended method for building the PDF files is to use the Docker Image, as described in the [RISC-V Docs Base Container Image repository](https://github.com/riscv/riscv-docs-base-container-image).
+
+Alternative build methods, such as local builds and GitHub Action builds, are also available and described in the Documentation Developer's Guide.
diff --git a/vendor/riscv/riscv-isa-manual/dependencies/Gemfile b/vendor/riscv/riscv-isa-manual/dependencies/Gemfile
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+source 'https://rubygems.org'
+gem 'asciidoctor'
+gem 'asciidoctor-bibtex'
+gem 'asciidoctor-diagram'
+gem 'asciidoctor-mathematical'
+gem 'asciidoctor-pdf'
+gem 'citeproc-ruby'
+gem 'coderay'
+gem 'csl-styles'
+gem 'json'
+gem 'pygments.rb'
+gem 'rghost'
+gem 'rouge'
+gem 'ruby_dev'
diff --git a/vendor/riscv/riscv-isa-manual/dependencies/README.md b/vendor/riscv/riscv-isa-manual/dependencies/README.md
@@ -0,0 +1,3 @@
+Dependencies for the build environment for various package managers.  Used in
+`.github/workflows/`.
+
diff --git a/vendor/riscv/riscv-isa-manual/dependencies/apt_packages.txt b/vendor/riscv/riscv-isa-manual/dependencies/apt_packages.txt
@@ -0,0 +1,22 @@
+bison
+build-essential
+cmake
+curl
+flex
+fonts-lyx
+git
+graphviz
+# For wavedrom
+default-jre
+libcairo2-dev
+libffi-dev
+libgdk-pixbuf2.0-dev
+libglib2.0-dev
+libpango1.0-dev
+libxml2-dev
+make
+pkg-config
+ruby
+ruby-dev
+libwebp-dev
+libzstd-dev
diff --git a/vendor/riscv/riscv-isa-manual/dependencies/package.json b/vendor/riscv/riscv-isa-manual/dependencies/package.json
@@ -0,0 +1,8 @@
+{
+  "name": "local",
+  "version": "0.0.1",
+  "dependencies": {
+    "wavedrom-cli": "^2.6.8",
+    "bytefield-svg": "^1.8.0"
+  }
+}
diff --git a/vendor/riscv/riscv-isa-manual/marchid.md b/vendor/riscv/riscv-isa-manual/marchid.md
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+Open-Source RISC-V Architecture IDs
+========================================
+
+Every RISC-V hart provides an marchid CSR that encodes its base
+microarchitecture.  Any hart may report an architecture ID of 0, indicating
+unspecified origin.  Commercial implementations (those with nonzero mvendorid)
+may encode any value in marchid with the most-significant bit set, with the
+low-order bits formatted in a vendor-specific manner.  Open-source
+implementations (which may or may not have a nonzero mvendorid) have the
+most-significant bit clear, with a globally unique pattern in the low-order
+bits.
+
+This document contains the canonical list of open-source RISC-V implementations
+and their architecture IDs.  Open-source project maintainers may make pull
+requests against this repository to request the allocation of an architecture
+ID.
+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
+Project Name  | Maintainers                     | Point of Contact                                            | Architecture ID   | Project URL                                         
+------------- | ------------------------------- | ----------------------------------------------------------- | ----------------- | --------------------------------------------------- 
+Rocket        | SiFive, UC Berkeley             | [Andrew Waterman](mailto:[email protected]), SiFive         | 1                 | https://github.com/chipsalliance/rocket-chip
+BOOM          | UC Berkeley                     | [Christopher Celio](mailto:[email protected])              | 2                 | https://github.com/riscv-boom/riscv-boom
+CVA6          | OpenHW Group                    | [Florian Zaruba](mailto:[email protected]), OpenHW Group | 3                 | https://github.com/openhwgroup/cva6             
+CV32E40P      | OpenHW Group                    | [Davide Schiavone](mailto:[email protected]), OpenHW Group | 4                 | https://github.com/openhwgroup/cv32e40p
+Spike         | SiFive, UC Berkeley             | [Andrew Waterman](mailto:[email protected]), SiFive         | 5                 | https://github.com/riscv/riscv-isa-sim              
+E-Class       | IIT Madras                      | [Neel Gala](mailto:[email protected])                      | 6                 | https://gitlab.com/shaktiproject/cores/e-class
+ORCA          | VectorBlox                      | [Joel Vandergriendt](mailto:[email protected])            | 7                 | https://github.com/vectorblox/orca
+SCR1          | Syntacore                       | [Dmitri Pavlov](mailto:[email protected]), Syntacore| 8               | https://github.com/syntacore/scr1
+YARVI         | Tommy Thorn's Priceless Services| [Tommy Thorn](mailto:[email protected])                | 9                 | https://github.com/tommythorn/yarvi
+RVBS          | Alexandre Joannou, University of Cambridge| [Alexandre Joannou](mailto:[email protected])    | 10                | https://github.com/CTSRD-CHERI/RVBS
+SweRV EH1     | Western Digital Corporation     | [Thomas Wicki](mailto:[email protected])                 | 11                | https://github.com/chipsalliance/Cores-SweRV
+MSCC          | Rongcui Dong                    | [Rongcui Dong](mailto:[email protected])                | 12 | https://github.com/rongcuid/MSCC
+BlackParrot   | The World                       | [Michael B. Taylor](mailto:[email protected]), U. Washington | 13 |  https://github.com/black-parrot 
+BaseJump Manycore   | U. Washington             | [Michael B. Taylor](mailto:[email protected]), U. Washington | 14 |  https://github.com/bespoke-silicon-group/bsg_manycore 
+C-Class       | IIT Madras                      | [Neel Gala](mailto:[email protected])                      | 15                 | https://gitlab.com/shaktiproject/cores/c-class
+SweRV EL2     | Western Digital Corporation     | [Thomas Wicki](mailto:[email protected])                 | 16                | https://github.com/chipsalliance/Cores-SweRV-EL2
+SweRV EH2     | Western Digital Corporation     | [Thomas Wicki](mailto:[email protected])                 | 17                | https://github.com/chipsalliance/Cores-SweRV-EH2
+SERV          | Olof Kindgren Enterprises       | [Olof Kindgren](mailto:[email protected])             | 18                | https://github.com/olofk/serv
+NEORV32       | Stephan Nolting                 | [Stephan Nolting](mailto:[email protected])               | 19                | https://github.com/stnolting/neorv32
+CV32E40X      | OpenHW Group                    | [Arjan Bink](mailto:[email protected]), Silicon Laboratories | 20           | https://github.com/openhwgroup/cv32e40x
+CV32E40S      | OpenHW Group                    | [Arjan Bink](mailto:[email protected]), Silicon Laboratories | 21           | https://github.com/openhwgroup/cv32e40s
+Ibex          | lowRISC                         | [lowRISC Hardware Team](mailto:[email protected])        | 22                | https://github.com/lowRISC/ibex
+RudolV        | Jörg Mische                     | [Jörg Mische](mailto:[email protected])                          | 23                | https://github.com/bobbl/rudolv
+Steel Core    | Rafael Calcada                  | [Rafael Calcada](mailto:[email protected])            | 24                | https://github.com/rafaelcalcada/steel-core
+XiangShan     | ICT, CAS                        | [XiangShan Team](mailto:[email protected])            | 25                | https://github.com/OpenXiangShan/XiangShan
+Hummingbirdv2 E203  | Nuclei System Technology  | [Can Hu](mailto:[email protected]), Nuclei System Technology  | 26            | https://github.com/riscv-mcu/e203_hbirdv2
+Hazard3       | Luke Wren                       | [Luke Wren](mailto:[email protected])                       | 27                | https://github.com/wren6991/hazard3
+CV32E41P      | OpenHW Group                    | [Mark Hill](mailto:[email protected]), OpenHW Group        | 28            | https://github.com/openhwgroup/cv32e41p
+Rift          | Jianhu Lab, WUT                 | [Ruige Lee](mailto:[email protected])                     | 29            | [RiftCore](https://github.com/whutddk/RiftCore), [Rift2Core](https://github.com/whutddk/Rift2Core)
+RISu064       | Wenting Zhang                   | [Wenting Zhang](mailto:[email protected])                 | 30                | https://github.com/zephray/RISu064
+AIRISC        | Fraunhofer IMS                  | [AIRISC Support](mailto:[email protected])           | 31               | https://github.com/Fraunhofer-IMS/airisc_core_complex
+Proteus       | imec-DistriNet, KU Leuven       | [Marton Bognar](mailto:[email protected])           | 32               | https://github.com/proteus-core/proteus
+VexRiscv      | SpinalHDL                       | [Charles Papon](mailto:[email protected])          | 33               | https://github.com/SpinalHDL/VexRiscv
+Shuttle       | UC Berkeley                     | [Jerry Zhao](mailto:[email protected])                 | 34               | https://github.com/ucb-bar/shuttle
+CV32E2        | OpenHW Group                    | [Davide Schiavone](mailto:[email protected]), OpenHW Group | 35                 | https://github.com/openhwgroup/cve2
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		Dependencies for the build environment for various package managers. Used in
		`.github/workflows/`.