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MarioOpenHWGroup committed Mar 21, 2024
1 parent 6566f4d commit 3ceb086
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2 changes: 0 additions & 2 deletions .gitlab-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -139,8 +139,6 @@ smoke:
- "vcs-testharness,spike"
- "vcs-uvm,spike"
script:
- source /opt/questa/questa_sim-2022.4_2/questasim/setup/bashrc
- PATH=$PATH:/opt/questa/questa_sim-2022.4_2/questasim/bin
- bash verif/regress/smoke-tests.sh
- !reference [.simu_after_script]

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2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -314,7 +314,7 @@ vcs: vcs_build
# Build the TB and module using QuestaSim
build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
# Optimize top level
$(VOPT) $(vopt_flags) -64 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis -dpilib $(SPIKE_INSTALL_DIR)/lib/libriscv -dpilib $(SPIKE_INSTALL_DIR)/lib/lifesvr -suppress 2085 -suppress 7063
$(VOPT) -64 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis -dpilib $(SPIKE_INSTALL_DIR)/lib/libriscv -dpilib $(SPIKE_INSTALL_DIR)/lib/lifesvr -suppress 2085 -suppress 7063

# src files
$(library)/.build-srcs: $(library)
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36 changes: 18 additions & 18 deletions corev_apu/tb/common/spike.sv
Original file line number Diff line number Diff line change
Expand Up @@ -108,24 +108,24 @@ module spike #(
s_core.csr_wdata[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wdata;\
s_core.csr_wmask[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wmask;

`GET_RVFI_CSR (CSR_MSTATUS , mstatus , 0)
`GET_RVFI_CSR (CSR_MCAUSE , mcause , 1)
`GET_RVFI_CSR (CSR_MEPC , mepc , 2)
`GET_RVFI_CSR (CSR_MTVEC , mtvec , 3)
`GET_RVFI_CSR (CSR_MISA , misa , 4)
`GET_RVFI_CSR (CSR_MTVAL , mtval , 5)
`GET_RVFI_CSR (CSR_MIDELEG , mideleg , 6)
`GET_RVFI_CSR (CSR_MEDELEG , medeleg , 7)
`GET_RVFI_CSR (CSR_SATP , satp , 8)
`GET_RVFI_CSR (CSR_MIE , mie , 9)
`GET_RVFI_CSR (CSR_STVEC , stvec ,10)
`GET_RVFI_CSR (CSR_SSCRATCH , sscratch ,11)
`GET_RVFI_CSR (CSR_SEPC , sepc ,12)
`GET_RVFI_CSR (CSR_MSCRATCH , mscratch ,13)
`GET_RVFI_CSR (CSR_STVAL , stval ,14)
`GET_RVFI_CSR (CSR_SCAUSE , scause ,15)
`GET_RVFI_CSR (CSR_PMPADDR0 , pmpaddr[0] ,16)
`GET_RVFI_CSR (CSR_PMPCFG0 , pmpcfg0 ,17)
`GET_RVFI_CSR (CSR_MSTATUS , mstatus , 0)
`GET_RVFI_CSR (CSR_MCAUSE , mcause , 1)
`GET_RVFI_CSR (CSR_MEPC , mepc , 2)
`GET_RVFI_CSR (CSR_MTVEC , mtvec , 3)
`GET_RVFI_CSR (CSR_MISA , misa , 4)
`GET_RVFI_CSR (CSR_MTVAL , mtval , 5)
`GET_RVFI_CSR (CSR_MIDELEG , mideleg , 6)
`GET_RVFI_CSR (CSR_MEDELEG , medeleg , 7)
`GET_RVFI_CSR (CSR_SATP , satp , 8)
`GET_RVFI_CSR (CSR_MIE , mie , 9)
`GET_RVFI_CSR (CSR_STVEC , stvec , 10)
`GET_RVFI_CSR (CSR_SSCRATCH , sscratch , 11)
`GET_RVFI_CSR (CSR_SEPC , sepc , 12)
`GET_RVFI_CSR (CSR_MSCRATCH , mscratch , 13)
`GET_RVFI_CSR (CSR_STVAL , stval , 14)
`GET_RVFI_CSR (CSR_SCAUSE , scause , 15)
`GET_RVFI_CSR (CSR_PMPADDR0 , pmpaddr[0] , 16)
`GET_RVFI_CSR (CSR_PMPCFG0 , pmpcfg0 , 17)

rvfi_spike_step(s_core, s_reference_model);
rvfi_compare(s_core, s_reference_model);
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5 changes: 0 additions & 5 deletions corev_apu/tb/rvfi_tracer.sv
Original file line number Diff line number Diff line change
Expand Up @@ -108,11 +108,6 @@ module rvfi_tracer #(
end else begin
if (rvfi_i[i].mem_wmask != 0) begin
$fwrite(f, " mem 0x%h 0x%h", rvfi_i[i].mem_addr, rvfi_i[i].mem_wdata);
if (TOHOST_ADDR != '0 &&
rvfi_i[i].mem_paddr == TOHOST_ADDR) begin
$fwrite(f, " mem 0x%h 0x%h", rvfi_i[i].mem_addr, rvfi_i[i].mem_wdata);
end

if (TOHOST_ADDR != '0 &&
rvfi_i[i].mem_paddr == TOHOST_ADDR &&
rvfi_i[i].mem_wdata[0] == 1'b1) begin
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6 changes: 3 additions & 3 deletions verif/regress/coremark.sh
Original file line number Diff line number Diff line change
Expand Up @@ -30,11 +30,11 @@ if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=veri-testharness
fi

if ! [ -n "$UVM_VERBOSITY_LEVEL" ]; then
UVM_VERBOSITY_LEVEL=UVM_NONE
if ! [ -n "$UVM_VERBOSITY" ]; then
UVM_VERBOSITY=UVM_NONE
fi

export DV_OPTS="$DV_OPTS --issrun_opts=\"+UVM_VERBOSITY=$UVM_VERBOSITY_LEVEL\""
export DV_OPTS="$DV_OPTS --issrun_opts=\"+UVM_VERBOSITY=$UVM_VERBOSITY\""

make clean
make -C verif/sim clean_all
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6 changes: 3 additions & 3 deletions verif/regress/smoke-tests.sh
Original file line number Diff line number Diff line change
Expand Up @@ -32,11 +32,11 @@ if ! [ -n "$DV_SIMULATORS" ]; then
DV_SIMULATORS=vcs-testharness,spike
fi

if ! [ -n "$UVM_VERBOSITY_LEVEL" ]; then
UVM_VERBOSITY_LEVEL=UVM_NONE
if ! [ -n "$UVM_VERBOSITY" ]; then
UVM_VERBOSITY=UVM_NONE
fi

export DV_OPTS="$DV_OPTS --issrun_opts=\"+UVM_VERBOSITY=$UVM_VERBOSITY_LEVEL\""
export DV_OPTS="$DV_OPTS --issrun_opts=\"+UVM_VERBOSITY=$UVM_VERBOSITY\""

cd verif/sim/
python3 cva6.py --testlist=../tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml --test rv32i-I-ADD-01 --iss_yaml cva6.yaml --target cv64a6_imafdc_sv39 --iss=$DV_SIMULATORS $DV_OPTS
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10 changes: 5 additions & 5 deletions verif/tb/core/custom_uvm_macros.svh
Original file line number Diff line number Diff line change
Expand Up @@ -49,12 +49,12 @@ parameter max_errors = 5;
static uvm_verbosity current_verbosity_level = UVM_LOW;

int string_to_verbosity_level [string] = '{
"UVM_NONE" : 0,
"UVM_LOW" : 100,
"UVM_NONE" : 0,
"UVM_LOW" : 100,
"UVM_MEDIUM" : 200,
"UVM_HIGH" : 300,
"UVM_FULL" : 400,
"UVM_DEBUG" : 500 };
"UVM_HIGH" : 300,
"UVM_FULL" : 400,
"UVM_DEBUG" : 500 };

function void uvm_set_verbosity_level(string verbosity);
$cast(current_verbosity_level,string_to_verbosity_level[verbosity]);
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3 changes: 0 additions & 3 deletions verif/tb/uvmt/uvmt_cva6_tb_ifs.sv
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,6 @@
`ifndef __UVMT_CVA6_TB_IFS_SV__
`define __UVMT_CVA6_TB_IFS_SV__


interface uvmt_rvfi_if #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_empty,
parameter type rvfi_instr_t = logic,
Expand All @@ -38,7 +37,6 @@ interface uvmt_rvfi_if #(

endinterface : uvmt_rvfi_if


interface uvmt_tb_exit_if (
output logic[31:0] tb_exit_o
);
Expand All @@ -47,5 +45,4 @@ interface uvmt_tb_exit_if (
end
endinterface : uvmt_tb_exit_if


`endif // __UVMT_CVA6_TB_IFS_SV__

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