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Spike TANDEM
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Makefile:
  * adding rvfi_pkg
  * adding absolute paths to the incdir to avoid relative path issues
  * move spike.sv from tbs to src

core/cva6.sv:
  * change tval for new instr field of the scoreboard_entry_t
  * change trap to support all kinds of exceptions and interrupts
core/decoder.sv:
  * change tval for 0 and add the old tval value to instr field
core/include/ariane_pkg.sv:
  * add instr field on scoreboard_entry_t
core/include/rvfi_pkg.sv:
  * new file that has:
    * st_rvfi struct, compare function, spike init function
corev_apu/tb/common/spike.sv
  * change module to support rvfi_pkg
verif/env/uvme/uvme_cva6_cfg.sv:
  * rename scooreboarding_enable to scoreboard_enable
  * rvfi_cfg.nret now properly set
verif/env/uvme/uvme_cva6_constants.sv:
  * delete RVFI_NRET to avoid misconfigurations
verif/env/uvme/uvme_cva6_env.sv:
  * rename scoreboarding
  * unify rvfi_monitors into one
verif/env/uvme/uvme_cva6_pkg.sv:
  * add cva6_config_pkg to be available in the components
verif/regress/install-spike.sh:
  * change SPIKE_SRC_DIR to core-v-verif
verif/sim/Makefile:
  * avoid reconfigure if a config.log exists
  * add core_v_verif variable
  * add spike-tandem variable
  * add elfloader lib instead of ariane_dpi
verif/sim/cva6.py:
  * solve trailing issues
verif/sim/cva6.yaml:
  * delete steps variable #TODO add new timeout impl
verif/sim/cva6_spike_log_to_trace_csv.py:
  * adapt for new spike impl
verif/tb/uvmt/cva6_tb_wrapper.sv:
  * PRELOAD to elf_file
verif/tb/uvmt/uvmt_cva6_pkg.sv:
  * add rvfi_pkg
verif/tb/uvmt/uvmt_cva6_tb.sv:
  * add localparam RVFI_NRET
  * add rvfi_cause
verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv:
  * add factory override for spike
  • Loading branch information
@MarioOpenHWGroup
MarioOpenHWGroup committed Oct 18, 2023
1 parent 01e5658 commit 296d991
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Showing 19 changed files with 169 additions and 277 deletions.
15 changes: 9 additions & 6 deletions Makefile
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Original file line number Diff line number Diff line change
Expand Up @@ -154,7 +154,8 @@ endif

# this list contains the standalone components
src := core/include/$(target)_config_pkg.sv \
core/include/rvfi_pkg.sv \
$(if $(spike-tandem),core/include/rvfi_pkg.sv) \
$(if $(spike-tandem),corev_apu/tb/common/spike.sv) \
corev_apu/src/ariane.sv \
$(wildcard corev_apu/bootrom/*.sv) \
$(wildcard corev_apu/clint/*.sv) \
Expand Down Expand Up @@ -224,7 +225,6 @@ fpga_src := $(addprefix $(root-dir), $(fpga_src))
# look for testbenches
tbs := core/include/$(target)_config_pkg.sv \
corev_apu/tb/ariane_tb.sv \
$(if $(spike-tandem),corev_apu/tb/common/spike.sv) \
corev_apu/tb/ariane_testharness.sv

tbs := $(addprefix $(root-dir), $(tbs))
Expand All @@ -245,7 +245,9 @@ riscv-fp-tests := $(shell xargs printf '\n%s' < $(riscv-fp-tests-list
riscv-benchmarks := $(shell xargs printf '\n%s' < $(riscv-benchmarks-list) | cut -b 1-)

# Search here for include files (e.g.: non-standalone components)
incdir := vendor/pulp-platform/common_cells/include/ vendor/pulp-platform/axi/include/ corev_apu/register_interface/include/
incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REPO_DIR)/vendor/pulp-platform/axi/include/ \
$(CVA6_REPO_DIR)/corev_apu/register_interface/include/ $(CVA6_REPO_DIR)/corev_apu/tb/common/ \
$(CVA6_REPO_DIR)/vendor/pulp-platform/axi/include/ $(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/

# Compile and sim flags
compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive -svinputport=compat +define+$(defines)
Expand Down Expand Up @@ -292,12 +294,12 @@ endif
vcs_build: $(dpi-library)/ariane_dpi.so
mkdir -p $(vcs-library)
cd $(vcs-library) &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -assert svaext -f ../core/Flist.cva6 &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) -assert svaext -f ../core/Flist.cva6 $(list_incdir) &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog +define+$(defines) $(filter %.sv,$(ariane_pkg)) +incdir+core/include/+$(VCS_HOME)/etc/uvm-1.2/dpi &&\
vhdlan $(if $(VERDI), -kdb,) -full64 -nc $(filter %.vhd,$(uart_src)) &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -assert svaext +define+$(defines) $(filter %.sv,$(src)) +incdir+../vendor/pulp-platform/common_cells/include/+../vendor/pulp-platform/axi/include/+../corev_apu/register_interface/include/ &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -assert svaext +define+$(defines) +incdir+$(VCS_HOME)/etc/uvm/src $(VCS_HOME)/etc/uvm/src/uvm_pkg.sv $(filter %.sv,$(src)) $(list_incdir) &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+$(defines) +incdir+../vendor/pulp-platform/axi/include/ &&\
vlogan $(if $(VERDI), -kdb,) -full64 -nc -sverilog -ntb_opts uvm-1.2 $(tbs) +define+$(defines) $(list_incdir) &&\
vcs $(if $(VERDI), -kdb -debug_access+all -lca,) -full64 -timescale=1ns/1ns -ntb_opts uvm-1.2 work.ariane_tb -error="IWNF"

vcs: vcs_build
Expand Down Expand Up @@ -603,6 +605,7 @@ verilate:
sim-verilator: verilate
$(ver-library)/Variane_testharness $(elf-bin)


$(addsuffix -verilator,$(riscv-asm-tests)): verilate
$(ver-library)/Variane_testharness $(riscv-test-dir)/$(subst -verilator,,$@)

Expand Down
14 changes: 7 additions & 7 deletions core/cva6.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1268,15 +1268,15 @@ module cva6 import ariane_pkg::*; #(
end
for (int i = 0; i < CVA6ExtendCfg.NrCommitPorts; i++) begin
if (commit_ack[i] && !commit_instr_id_commit[i].ex.valid) begin
$fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]);
$fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].instr[31:0], commit_instr_id_commit[i].instr[31:0]);
end else if (commit_ack[i] && commit_instr_id_commit[i].ex.valid) begin
if (commit_instr_id_commit[i].ex.cause == 2) begin
$fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc);
$fwrite(f, "Exception Cause: Illegal Instructions, DASM(%h) PC=%h\n", commit_instr_id_commit[i].instr[31:0], commit_instr_id_commit[i].pc);
end else begin
if (debug_mode) begin
$fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].ex.tval[31:0]);
$fwrite(f, "%d 0x%0h %s (0x%h) DASM(%h)\n", cycles, commit_instr_id_commit[i].pc, mode, commit_instr_id_commit[i].instr[31:0], commit_instr_id_commit[i].instr[31:0]);
end else begin
$fwrite(f, "Exception Cause: %5d, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.cause, commit_instr_id_commit[i].ex.tval[31:0], commit_instr_id_commit[i].pc);
$fwrite(f, "Exception Cause: %5d, DASM(%h) PC=%h\n", commit_instr_id_commit[i].ex.cause, commit_instr_id_commit[i].instr[31:0], commit_instr_id_commit[i].pc);
end
end
end
Expand Down Expand Up @@ -1312,10 +1312,10 @@ module cva6 import ariane_pkg::*; #(
(exception && (ex_commit.cause == riscv::ENV_CALL_MMODE ||
ex_commit.cause == riscv::ENV_CALL_SMODE ||
ex_commit.cause == riscv::ENV_CALL_UMODE));
rvfi_o[i].insn = ex_commit.valid ? ex_commit.tval[31:0] : commit_instr_id_commit[i].ex.tval[31:0];
rvfi_o[i].insn = commit_instr_id_commit[i].instr[31:0];
// when trap, the instruction is not executed
rvfi_o[i].trap = mem_exception;
rvfi_o[i].cause = ex_commit.cause;
rvfi_o[i].trap = exception;
rvfi_o[i].cause = commit_instr_id_commit[i].ex.cause;
rvfi_o[i].mode = debug_mode ? 2'b10 : priv_lvl;
rvfi_o[i].ixl = riscv::XLEN == 64 ? 2 : 1;
rvfi_o[i].rs1_addr = commit_instr_id_commit[i].rs1[4:0];
Expand Down
4 changes: 3 additions & 1 deletion core/decoder.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -1276,7 +1276,9 @@ module decoder import ariane_pkg::*; #(
if (~ex_i.valid) begin
// if we didn't already get an exception save the instruction here as we may need it
// in the commit stage if we got a access exception to one of the CSR registers
instruction_o.ex.tval = (is_compressed_i) ? {{riscv::XLEN-16{1'b0}}, compressed_instr_i} : {{riscv::XLEN-32{1'b0}}, instruction_i};
//instruction_o.ex.tval = (is_compressed_i) ? {{riscv::XLEN-16{1'b0}}, compressed_instr_i} : {{riscv::XLEN-32{1'b0}}, instruction_i};
instruction_o.instr = (is_compressed_i) ? {{riscv::XLEN-16{1'b0}}, compressed_instr_i} : {{riscv::XLEN-32{1'b0}}, instruction_i};
instruction_o.ex.tval = 'h0;
// instructions which will throw an exception are marked as valid
// e.g.: they can be committed anytime and do not need to wait for any functional unit
// check here if we decoded an invalid instruction or if the compressed decoder already decoded
Expand Down
2 changes: 1 addition & 1 deletion core/include/ariane_pkg.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,6 @@ package ariane_pkg;
localparam ASID_WIDTH = (riscv::XLEN == 64) ? 16 : 1;
localparam BITS_SATURATION_COUNTER = 2;

localparam ENABLE_RENAME = cva6_config_pkg::CVA6ConfigRenameEn;
localparam ISSUE_WIDTH = 1;

// depth of store-buffers, this needs to be a power of two
Expand Down Expand Up @@ -530,6 +529,7 @@ package ariane_pkg;

typedef struct packed {
logic [riscv::VLEN-1:0] pc; // PC of instruction
riscv::xlen_t instr; // Instruction value
logic [TRANS_ID_BITS-1:0] trans_id; // this can potentially be simplified, we could index the scoreboard entry
// with the transaction id in any case make the width more generic
fu_t fu; // functional unit to use
Expand Down
53 changes: 8 additions & 45 deletions core/include/rvfi_pkg.sv
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Original file line number Diff line number Diff line change
@@ -1,53 +1,16 @@
`ifndef __UVMA_RVFI_TDEFS_SV__
`define __UVMA_RVFI_TDEFS_SV__
`ifndef __UVMA_RVFI_PKG_SV__
`define __UVMA_RVFI_PKG_SV__

package rvfi_pkg;

typedef struct {
longint unsigned nret_id;
longint unsigned cycle_cnt;
longint unsigned order;
longint unsigned insn;
byte unsigned trap;
byte unsigned halt;
byte unsigned intr;
int unsigned mode;
int unsigned ixl;
int unsigned dbg;
int unsigned dbg_mode;
longint unsigned nmip;

longint unsigned insn_interrupt;
longint unsigned insn_interrupt_id;
longint unsigned insn_bus_fault;
longint unsigned insn_nmi_store_fault;
longint unsigned insn_nmi_load_fault;

longint unsigned pc_rdata;
longint unsigned pc_wdata;

longint unsigned rs1_addr;
longint unsigned rs1_rdata;

longint unsigned rs2_addr;
longint unsigned rs2_rdata;

longint unsigned rs3_addr;
longint unsigned rs3_rdata;

longint unsigned rd1_addr;
longint unsigned rd1_wdata;
package rvfi_pkg;

longint unsigned rd2_addr;
longint unsigned rd2_wdata;
`include "uvm_macros.svh"
import uvm_pkg::*;

longint unsigned mem_addr;
longint unsigned mem_rdata;
longint unsigned mem_rmask;
longint unsigned mem_wdata;
longint unsigned mem_wmask;
`include "uvma_rvfi_constants.sv"
`include "uvma_rvfi_tdefs.sv"
`include "uvma_rvfi_utils.sv"

} st_rvfi;
endpackage

`endif
162 changes: 30 additions & 132 deletions corev_apu/tb/common/spike.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -13,20 +13,14 @@
// Description: Wrapped Spike Model for Tandem Verification

import ariane_pkg::*;
import uvm_pkg::*;
import rvfi_pkg::*;

`include "uvm_macros.svh"
import "DPI-C" function int spike_create(string filename);

import "DPI-C" function void spike_set_param_uint64_t(string base, string name, longint unsigned value);
import "DPI-C" function void spike_set_param_str(string base, string name, string value);
import "DPI-C" function void spike_set_default_params(string profile);

import "DPI-C" function void spike_step(output st_rvfi rvfi);
import "DPI-C" function void spike_step(inout st_rvfi rvfi);

module spike #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = config_pkg::cva6_cfg_default,
parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
parameter type rvfi_instr_t = struct packed {
logic [config_pkg::NRET-1:0] valid;
logic [config_pkg::NRET*64-1:0] order;
Expand Down Expand Up @@ -58,150 +52,54 @@ module spike #(
input logic clk_i,
input logic rst_ni,
input logic clint_tick_i,
input rvfi_instr_t[CVA6Cfg.NrCommitPorts:1-0] rvfi_i
input rvfi_instr_t[CVA6Cfg.NrCommitPorts-1:0] rvfi_i
);
static uvm_cmdline_processor uvcl = uvm_cmdline_processor::get_inst();
string binary = "";
string rtl_isa = "";

logic fake_clk;
logic clint_tick_q, clint_tick_qq, clint_tick_qqq, clint_tick_qqqq;

initial begin
`uvm_info("Spike Tandem", "Setting up Spike...", UVM_NONE);
void'(uvcl.get_arg_value("+PRELOAD=", binary));
assert(binary != "") else $error("We need a preloaded binary for tandem verification");
// ISA string format: RV<XLEN>IM?A?C?F?D?C?(_<ext>)* (FORNOW no RV64GC)
// Base string
rtl_isa = $sformatf("RV%-2dIM%s%s%s%s",
riscv::XLEN,
CVA6Cfg.RVA ? "A" : "",
CVA6Cfg.RVF ? "F" : "",
CVA6Cfg.RVD ? "D" : "",
CVA6Cfg.RVC ? "C" : "");
// TODO Fixme
//if (CVA6Cfg.CVA6ConfigBExtEn) begin
// rtl_isa = $sformatf("%s_zba_zbb_zbc_zbs", rtl_isa);
//end
// TODO: build the ISA string with extensions
void'(spike_set_default_params("cva6"));
void'(spike_set_param_uint64_t("/top/core/0/", "boot_addr", 'h10000));
void'(spike_set_param_str("/top/", "isa", rtl_isa));
void'(spike_set_param_str("/top/core/0/", "isa", rtl_isa));
void'(spike_create(binary));

rvfi_initialize_spike('h1);
end

st_rvfi rvfi;
st_rvfi t_core, t_reference_model;
logic [63:0] pc64;
logic [31:0] rtl_instr;
logic [31:0] spike_instr;
string cause;
const string format_instr_str = "%15s | RVFI | %8d | %6d | %8x | %8x | %x | x%-8x | %-8x | x%-16x | %-16x | x%-8x | %-8x";
string instr;

always_ff @(posedge clk_i) begin
if (rst_ni) begin

for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
pc64 = {{riscv::XLEN-riscv::VLEN{rvfi_i[i].pc_rdata[riscv::VLEN-1]}}, rvfi_i[i].pc_rdata};

if (rvfi_i[i].trap) begin
`ifdef SPIKE_MISSING_DATA
assert (rvfi.trap === rvfi_i[i].trap) else begin
$warning("\x1B[38;5;221m[Tandem] Exception not detected\x1B[0m");
$display("\x1B[91mCVA6: %p\x1B[0m", rvfi_i[i].trap);
$display("\x1B[91mSpike: %p\x1B[0m", rvfi.trap);
$finish;
end
`endif
case (rvfi_i[i].cause)
32'h0 : cause = "INSTR_ADDR_MISALIGNED";
32'h1 : cause = "INSTR_ACCESS_FAULT";
32'h2 : cause = "ILLEGAL_INSTR";
32'h3 : cause = "BREAKPOINT";
32'h4 : cause = "LD_ADDR_MISALIGNED";
32'h5 : cause = "LD_ACCESS_FAULT";
32'h6 : cause = "ST_ADDR_MISALIGNED";
32'h7 : cause = "ST_ACCESS_FAULT";
32'h8 : cause = "USER_ECALL";
32'h9 : cause = "SUPERVISOR_ECALL";
32'ha : cause = "VIRTUAL_SUPERVISOR_ECALL";
32'hb : cause = "MACHINE_ECALL";
32'hc : cause = "FETCH_PAGE_FAULT";
32'hd : cause = "LOAD_PAGE_FAULT";
32'hf : cause = "STORE_PAGE_FAULT";
32'h14: cause = "FETCH_GUEST_PAGE_FAULT";
32'h15: cause = "LOAD_GUEST_PAGE_FAULT";
32'h16: cause = "VIRTUAL_INSTRUCTION";
32'h17: cause = "STORE_GUEST_PAGE_FAULT";
default: $error("[Spike Tandem] *** Unhandled trap ID %d (0x%h)\n",
rvfi_i[i].cause, rvfi_i[i].cause);
endcase;

$display("\x1B[91mCVA6 exception %s at 0x%h\n", cause, pc64);
spike_step(rvfi);
end
if (rvfi_i[i].valid) begin
spike_step(rvfi);
spike_instr = (rvfi.insn[1:0] != 2'b11) ? {16'b0, rvfi.insn[15:0]} : rvfi.insn;
rtl_instr = rvfi_i[i].insn;
// $display("[Spike Tandem] commit_log = %p", commit_log);
// $display("\x1B[32mSpike: PC = 0x%h, instr = 0x%h\x1B[0m", commit_log.pc, spike_instr);
// $display("\x1B[91mCVA6: PC = 0x%h, instr = 0x%h\x1B[0m", pc64, rtl_instr);
assert (rvfi.pc_rdata === pc64) else begin
$warning("\x1B[38;5;221m[Tandem] PC Mismatch\x1B[0m");
$display("\x1B[91mSpike: 0x%16h\x1B[0m", rvfi.pc_rdata);
$display("\x1B[91mCVA6: 0x%16h\x1B[0m", pc64);
$finish;
end
if (!rvfi_i[i].trap) begin
assert (rvfi.mode === rvfi_i[i].mode) else begin
$warning("\x1B[38;5;221m[Tandem] Privilege level mismatch\x1B[0m");
$display("\x1B[91mSpike: %2d @ PC 0x%16h\x1B[0m", rvfi.mode, rvfi.pc_rdata);
$display("\x1B[91mCVA6: %2d @ PC 0x%16h\x1B[0m", rvfi_i[i].mode, pc64);
$finish;
end

assert (spike_instr === rtl_instr) else begin
$warning("\x1B[38;5;221m[Tandem] Decoded instruction mismatch\x1B[0m");
$display("\x1B[91m0x%h != 0x%h @ PC 0x%h\x1B[0m", rtl_instr, spike_instr, rvfi.pc_rdata);
$finish;
end

// TODO(zarubaf): Adapt for floating point instructions
if (rvfi_i[i].rd_addr != 0) begin
// check the return value
// $display("\x1B[37m%h === %h\x1B[0m", commit_instr_i[i].rd, commit_log.rd);
assert (rvfi_i[i].rd_addr[4:0] === rvfi.rd1_addr[4:0]) else begin
$warning("\x1B[38;5;221m[Tandem] Destination register mismatch\x1B[0m");
$display("\x1B[91mSpike: x%-4d @ PC 0x%16h\x1B[0m",
rvfi.rd1_addr[4:0], rvfi.pc_rdata);
$display("\x1B[91mCVA6: x%-4d @ PC 0x%16h\x1B[0m",
rvfi_i[i].rd_addr[4:0], pc64);
$finish;
end
assert (rvfi_i[i].rd_wdata === rvfi.rd1_wdata) else begin
$warning("\x1B[38;5;221m[Tandem] Write back data mismatch\x1B[0m");
$display("\x1B[91mSpike: x%-4d <- 0x%16h @ PC 0x%16h\x1B[0m",
rvfi.rd1_wdata[4:0], rvfi.rd1_wdata, rvfi.pc_rdata);
$display("\x1B[91mCVA6: x%-4d <- 0x%16h @ PC 0x%16h\x1B[0m",
rvfi_i[i].rd_addr[4:0], rvfi_i[i].rd_wdata, pc64);
$finish;
end
end
end

instr = $sformatf(format_instr_str, $sformatf("%t", $time),
rvfi.cycle_cnt,
rvfi.order,
rvfi.pc_rdata,
rvfi.insn,
rvfi.mode,
rvfi.rs1_addr, rvfi.rs1_rdata,
rvfi.rs2_addr, rvfi.rs2_rdata,
rvfi.rd1_addr, rvfi.rd1_wdata);
$display(instr);
if (rvfi_i[i].valid || rvfi_i[i].trap) begin
spike_step(t_reference_model);
t_core.order = rvfi_i[i].order;
t_core.insn = rvfi_i[i].insn;
t_core.trap = rvfi_i[i].trap;
t_core.cause = rvfi_i[i].cause;
t_core.halt = rvfi_i[i].halt;
t_core.intr = rvfi_i[i].intr;
t_core.mode = rvfi_i[i].mode;
t_core.ixl = rvfi_i[i].ixl;
t_core.rs1_addr = rvfi_i[i].rs1_addr;
t_core.rs2_addr = rvfi_i[i].rs2_addr;
t_core.rs1_rdata = rvfi_i[i].rs1_rdata;
t_core.rs2_rdata = rvfi_i[i].rs2_rdata;
t_core.rd1_addr = rvfi_i[i].rd_addr;
t_core.rd1_wdata = rvfi_i[i].rd_wdata;
t_core.pc_rdata = rvfi_i[i].pc_rdata;
t_core.pc_wdata = rvfi_i[i].pc_wdata;
t_core.mem_addr = rvfi_i[i].mem_addr;
t_core.mem_rmask = rvfi_i[i].mem_rmask;
t_core.mem_wmask = rvfi_i[i].mem_wmask;
t_core.mem_rdata = rvfi_i[i].mem_rdata;
t_core.mem_wdata = rvfi_i[i].mem_wdata;

rvfi_compare(t_core, t_reference_model);
end
end
end
Expand Down
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