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Bump verif/core-v-verif from d466330 to d94f0de
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Adapt to new core-v-verif
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dependabot[bot] authored and MarioOpenHWGroup committed Mar 20, 2024
1 parent 806a66c commit 230413b
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Showing 37 changed files with 385 additions and 115 deletions.
7 changes: 3 additions & 4 deletions .github/workflows/ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ jobs:
env:
NUM_JOBS: 8
steps:
- uses: actions/checkout@v2
- uses: actions/checkout@v4
with:
submodules: recursive

Expand Down Expand Up @@ -61,7 +61,7 @@ jobs:
needs:
build-riscv-tests
steps:
- uses: actions/checkout@v2
- uses: actions/checkout@v4
with:
submodules: recursive

Expand Down Expand Up @@ -101,9 +101,8 @@ jobs:
DV_SIMULATORS=${{matrix.target}} bash verif/regress/${{matrix.testcase}}.sh
- name: Upload Lint Report to Github
uses: actions/upload-artifact@v3
uses: actions/upload-artifact@v4
with:
name: ${{matrix.target}}.${{matrix.testcase}}
path: 'verif/sim/out*'
retention-days: 10
compression-level: 9
2 changes: 2 additions & 0 deletions .gitlab-ci.yml
Original file line number Diff line number Diff line change
Expand Up @@ -138,6 +138,8 @@ smoke:
- "veri-testharness,spike"
- "vcs-testharness,spike"
- "vcs-uvm,spike"
- "questa-testharness,spike"
- "questa-uvm,spike"
script:
- bash verif/regress/smoke-tests.sh
- !reference [.simu_after_script]
Expand Down
34 changes: 22 additions & 12 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -84,6 +84,7 @@ endif
ifneq ($(spike-tandem),)
compile_flag += -define SPIKE_TANDEM
CFLAGS += -I. -I$(SPIKE_INSTALL_DIR)/include/riscv
CFLAGS += -I. -I$(SPIKE_INSTALL_DIR)/include/disasm
defines += +SPIKE_TANDEM=1
endif

Expand Down Expand Up @@ -148,6 +149,8 @@ src := core/include/$(target)_config_pkg.sv
$(if $(spike-tandem),verif/tb/core/uvma_core_cntrl_pkg.sv) \
$(if $(spike-tandem),verif/tb/core/uvma_cva6pkg_utils_pkg.sv) \
$(if $(spike-tandem),verif/tb/core/uvma_rvfi_pkg.sv) \
$(if $(spike-tandem),verif/tb/core/uvmc_rvfi_reference_model_pkg.sv) \
$(if $(spike-tandem),verif/tb/core/uvmc_rvfi_scoreboard_pkg.sv) \
$(if $(spike-tandem),corev_apu/tb/common/spike.sv) \
corev_apu/src/ariane.sv \
$(wildcard corev_apu/bootrom/*.sv) \
Expand Down Expand Up @@ -215,7 +218,7 @@ fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/b
fpga_src := $(addprefix $(root-dir), $(fpga_src))

# look for testbenches
tbs := core/include/$(target)_config_pkg.sv corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv core/cva6_rvfi.sv
tbs := corev_apu/tb/ariane_tb.sv corev_apu/tb/ariane_testharness.sv core/cva6_rvfi.sv

tbs := $(addprefix $(root-dir), $(tbs))

Expand All @@ -239,15 +242,19 @@ incdir := $(CVA6_REPO_DIR)/vendor/pulp-platform/common_cells/include/ $(CVA6_REP
$(CVA6_REPO_DIR)/corev_apu/register_interface/include/ $(CVA6_REPO_DIR)/corev_apu/tb/common/ \
$(CVA6_REPO_DIR)/vendor/pulp-platform/axi/include/ \
$(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_rvfi/ \
$(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_reference_model/ \
$(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_components/uvmc_rvfi_scoreboard/ \
$(CVA6_REPO_DIR)/verif/core-v-verif/lib/uvm_agents/uvma_core_cntrl/ \
$(CVA6_REPO_DIR)/verif/tb/core/ \
$(CVA6_REPO_DIR)/core/include/
$(CVA6_REPO_DIR)/core/include/ \
$(SPIKE_INSTALL_DIR)/include/disasm/

# Compile and sim flags
compile_flag += +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive -svinputport=compat +define+$(defines)
compile_flag += -incr -64 -nologo -quiet -suppress 13262 -suppress 8607 -permissive -svinputport=compat +define+$(defines) -suppress 8386
vopt_flag += -incr -64 -nologo -quiet -suppress 13262 -permissive -svinputport=compat -t 1ns

uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=LOW
questa-flags += -t 1ns -64 -coverage -classdebug $(gui-sim) $(QUESTASIM_FLAGS) +tohost_addr=$(tohost_addr)
uvm-flags += +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW
questa-flags += -t 1ns -64 $(gui-sim) $(QUESTASIM_FLAGS) +tohost_addr=$(tohost_addr) +define+QUESTA
compile_flag_vhd += -64 -nologo -quiet -2008

# Iterate over all include directories and write them with +incdir+ prefixed
Expand All @@ -263,10 +270,12 @@ riscv-torture-bin := java -jar sbt-launch.jar
# if defined, calls the questa targets in batch mode
ifdef batch-mode
questa-flags += -c
questa-cmd += -do "run -all;"
endif
ifdef cov-mode
compile_flags += +cover=bcfst+/dut
questa-flags += -coverage
questa-cmd := -do "coverage save -onexit tmp/[email protected]; run -a; quit -code [coverage attribute -name TESTSTATUS -concise]"
questa-cmd += -do " log -r /*; run -all;"
else
questa-cmd := -do " log -r /*; run -all;"
endif
# we want to preload the memories
ifdef preload
Expand Down Expand Up @@ -305,7 +314,7 @@ vcs: vcs_build
# Build the TB and module using QuestaSim
build: $(library) $(library)/.build-srcs $(library)/.build-tb $(dpi-library)/ariane_dpi.so
# Optimize top level
$(VOPT) $(compile_flag) -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis
$(VOPT) $(vopt_flags) -64 -work $(library) $(top_level) -o $(top_level)_optimized +acc -check_synthesis -dpilib $(SPIKE_INSTALL_DIR)/lib/libriscv -dpilib $(SPIKE_INSTALL_DIR)/lib/lifesvr -suppress 2085 -suppress 7063

# src files
$(library)/.build-srcs: $(library)
Expand Down Expand Up @@ -345,8 +354,9 @@ generate-trace-vsim:

sim: build
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +MAX_CYCLES=$(max_cycles) +UVM_TESTNAME=$(test_case) \
+BASEDIR=$(riscv-test-dir) $(uvm-flags) $(QUESTASIM_FLAGS) -gblso $(SPIKE_INSTALL_DIR)/lib/libfesvr.so -sv_lib $(dpi-library)/ariane_dpi \
${top_level}_optimized +permissive-off ++$(elf_file) ++$(target-options) | tee sim.log
+BASEDIR=$(riscv-test-dir) $(uvm-flags) -sv_lib $(SPIKE_INSTALL_DIR)/lib/libriscv -sv_lib $(SPIKE_INSTALL_DIR)/lib/libfesvr \
-sv_lib $(SPIKE_INSTALL_DIR)/lib/libdisasm \
${top_level}_optimized +permissive-off +elf_file=$(elf_file) ++$(elf_file) ++$(target-options)

$(riscv-asm-tests): build
$(VSIM) +permissive $(questa-flags) $(questa-cmd) -lib $(library) +max-cycles=$(max_cycles) +UVM_TESTNAME=$(test_case) \
Expand Down Expand Up @@ -573,7 +583,7 @@ verilate_command := $(verilator) --no-timing verilator_config.vlt
$(if $(DEBUG), --trace-structs,) \
$(if $(TRACE_COMPACT), --trace-fst $(VL_INC_DIR)/verilated_fst_c.cpp) \
$(if $(TRACE_FAST), --trace $(VL_INC_DIR)/verilated_vcd_c.cpp) \
-LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_INSTALL_DIR)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_INSTALL_DIR)/lib -lfesvr -lriscv $(if $(PROFILE), -g -pg,) -lpthread $(if $(TRACE_COMPACT), -lz,)" \
-LDFLAGS "-L$(RISCV)/lib -L$(SPIKE_INSTALL_DIR)/lib -Wl,-rpath,$(RISCV)/lib -Wl,-rpath,$(SPIKE_INSTALL_DIR)/lib -lfesvr -lriscv -ldisasm $(if $(PROFILE), -g -pg,) -lpthread $(if $(TRACE_COMPACT), -lz,)" \
-CFLAGS "$(CFLAGS)$(if $(PROFILE), -g -pg,) -DVL_DEBUG -I$(SPIKE_INSTALL_DIR)" \
$(if $(SPIKE_TANDEM), +define+SPIKE_TANDEM, ) \
--cc --vpi \
Expand Down
7 changes: 7 additions & 0 deletions ci/setup.sh
Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,13 @@ if [ -d ${VERILATOR_BUILD_DIR} ]; then
make -C ${VERILATOR_BUILD_DIR} clean
fi

if [ -f ${SPIKE_PATH}/spike ]; then
spike_version="$(git -C ${SPIKE_SRC_DIR} log -1 --pretty=tformat:%h -- ${SPIKE_SRC_DIR}/..)"
spike_installed_version="$(${SPIKE_PATH}/spike -v |& cut -d ' ' -f 2)"
if [ "$spike_installed_version" != "$spike_version" ]; then
rm -rf ${SPIKE_INSTALL_DIR}
fi
fi
source verif/regress/install-spike.sh
if [ -d ${SPIKE_SRC_DIR}/build/ ]; then
make -C ${SPIKE_SRC_DIR}/build clean
Expand Down
8 changes: 6 additions & 2 deletions core/commit_stage.sv
Original file line number Diff line number Diff line change
Expand Up @@ -292,8 +292,12 @@ module commit_stage
end
end
end
if (CVA6Cfg.RVZCMP)
commit_macro_ack_o = (commit_instr_i[0].is_macro_instr || commit_instr_i[1].is_macro_instr) ? commit_macro_ack : commit_ack_o;
if (CVA6Cfg.RVZCMP) begin
if (CVA6Cfg.NrCommitPorts > 1)
commit_macro_ack_o = (commit_instr_i[0].is_macro_instr || commit_instr_i[1].is_macro_instr) ? commit_macro_ack : commit_ack_o;
else
commit_macro_ack_o = (commit_instr_i[0].is_macro_instr) ? commit_macro_ack : commit_ack_o;
end
else commit_macro_ack_o = commit_ack_o;
end

Expand Down
4 changes: 0 additions & 4 deletions core/cva6_rvfi_probes.sv
Original file line number Diff line number Diff line change
Expand Up @@ -127,7 +127,3 @@ module cva6_rvfi_probes

endmodule





6 changes: 3 additions & 3 deletions core/include/config_pkg.sv
Original file line number Diff line number Diff line change
Expand Up @@ -98,7 +98,7 @@ package config_pkg;
int unsigned NrScoreboardEntries;
// Address to jump when halt request
logic [63:0] HaltAddress;
// Address to jump when exception
// Address to jump when exception
logic [63:0] ExceptionAddress;
// Return address stack depth
int unsigned RASDepth;
Expand Down Expand Up @@ -288,8 +288,8 @@ package config_pkg;
// pragma translate_off
`ifndef VERILATOR
assert (Cfg.RASDepth > 0);
assert (2 ** $clog2(Cfg.BTBEntries) == Cfg.BTBEntries);
assert (2 ** $clog2(Cfg.BHTEntries) == Cfg.BHTEntries);
assert (Cfg.BTBEntries == 0 || (2 ** $clog2(Cfg.BTBEntries) == Cfg.BTBEntries));
assert (Cfg.BHTEntries == 0 || (2 ** $clog2(Cfg.BHTEntries) == Cfg.BHTEntries));
assert (Cfg.NrNonIdempotentRules <= NrMaxRules);
assert (Cfg.NrExecuteRegionRules <= NrMaxRules);
assert (Cfg.NrCachedRegionRules <= NrMaxRules);
Expand Down
1 change: 0 additions & 1 deletion corev_apu/tb/ariane_tb.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,6 @@ void handle_sigterm(int sig) {


extern "C" void read_elf(const char* filename);
extern "C" int64_t read_symbol(const char* symbol, uint64_t* address);
extern "C" char get_section (long long* address, long long* len);
extern "C" void read_section_void(long long address, void * buffer, uint64_t size = 0);

Expand Down
5 changes: 4 additions & 1 deletion corev_apu/tb/ariane_tb.sv
Original file line number Diff line number Diff line change
Expand Up @@ -23,9 +23,12 @@ import uvm_pkg::*;
`define MAIN_MEM(P) dut.i_sram.gen_cut[0].i_tc_sram_wrapper.i_tc_sram.init_val[(``P``)]
// `define USER_MEM(P) dut.i_sram.gen_cut[0].gen_mem.gen_mem_user.i_tc_sram_wrapper_user.i_tc_sram.init_val[(``P``)]

import "DPI-C" function read_elf(input string filename);
`ifndef READ_ELF_T
`define READ_ELF_T
import "DPI-C" function void read_elf(input string filename);
import "DPI-C" function byte get_section(output longint address, output longint len);
import "DPI-C" context function void read_section_sv(input longint address, inout byte buffer[]);
`endif

module ariane_tb;

Expand Down
12 changes: 7 additions & 5 deletions corev_apu/tb/ariane_testharness.sv
Original file line number Diff line number Diff line change
Expand Up @@ -617,7 +617,7 @@ module ariane_testharness #(
rvfi_probes_t rvfi_probes;
rvfi_csr_t rvfi_csr;
rvfi_instr_t [CVA6Cfg.NrCommitPorts-1:0] rvfi_instr;

ariane #(
.CVA6Cfg ( CVA6Cfg ),
.rvfi_probes_instr_t ( rvfi_probes_instr_t ),
Expand Down Expand Up @@ -664,8 +664,8 @@ module ariane_testharness #(
end
end



cva6_rvfi #(
.CVA6Cfg (CVA6Cfg),
.rvfi_instr_t(rvfi_instr_t),
Expand Down Expand Up @@ -700,12 +700,14 @@ module ariane_testharness #(
`ifdef SPIKE_TANDEM
spike #(
.CVA6Cfg ( CVA6Cfg ),
.rvfi_instr_t(rvfi_instr_t)
.rvfi_instr_t(rvfi_instr_t),
.rvfi_csr_t(rvfi_csr_t)
) i_spike (
.clk_i,
.rst_ni,
.clint_tick_i ( rtc_i ),
.rvfi_i ( rvfi_instr )
.rvfi_i ( rvfi_instr ),
.rvfi_csr_i ( rvfi_csr )
);
initial begin
$display("Running binary in tandem mode");
Expand Down
101 changes: 77 additions & 24 deletions corev_apu/tb/common/spike.sv
Original file line number Diff line number Diff line change
Expand Up @@ -12,34 +12,52 @@
// Date: 3/11/2018
// Description: Wrapped Spike Model for Tandem Verification

// Pre-processor macros
`ifdef VERILATOR
`include "custom_uvm_macros.svh"
`else
`include "uvm_macros.svh"
`endif

import ariane_pkg::*;
import riscv::*;
import uvma_rvfi_pkg::*;
import uvma_core_cntrl_pkg::*;
import uvmc_rvfi_reference_model_pkg::*;
import uvmc_rvfi_scoreboard_pkg::*;
import uvma_cva6pkg_utils_pkg::*;

module spike #(
parameter config_pkg::cva6_cfg_t CVA6Cfg = cva6_config_pkg::cva6_cfg,
parameter type rvfi_instr_t = logic,
parameter type rvfi_csr_t = logic,
parameter longint unsigned DramBase = 'h8000_0000,
parameter int unsigned Size = 64 * 1024 * 1024 // 64 Mega Byte
)(
input logic clk_i,
input logic rst_ni,
input logic clint_tick_i,
input rvfi_instr_t[CVA6Cfg.NrCommitPorts-1:0] rvfi_i
input rvfi_instr_t[CVA6Cfg.NrCommitPorts-1:0] rvfi_i,
input rvfi_csr_t rvfi_csr_i
);
string binary = "";
string rtl_isa = "";

st_core_cntrl_cfg st;

initial begin
st_core_cntrl_cfg st = cva6pkg_to_core_cntrl_cfg(st);
st = cva6pkg_to_core_cntrl_cfg(st);
st.boot_addr_valid = 1'b1;
st.boot_addr = 64'h0x10000;

rvfi_initialize(st);
rvfi_initialize_spike("cva6", st);

end

// There is a need of delayed rvfi as the 'csr'_q signal does not have the
// written value
rvfi_instr_t[CVA6Cfg.NrCommitPorts-1:0] rvfi_q;
st_rvfi s_core, s_reference_model;
logic [63:0] pc64;
logic [31:0] rtl_instr;
Expand All @@ -49,30 +67,65 @@ module spike #(

always_ff @(posedge clk_i) begin
if (rst_ni) begin
rvfi_q <= rvfi_i;
end
end

always_ff @(posedge clk_i) begin
if (rst_ni) begin

for (int i = 0; i < CVA6Cfg.NrCommitPorts; i++) begin
longint unsigned index = 0;

if (rvfi_q[i].valid || rvfi_q[i].trap) begin
s_core.order = rvfi_q[i].order;
s_core.insn = rvfi_q[i].insn;
s_core.trap = rvfi_q[i].trap;
s_core.trap |= (rvfi_q[i].cause << 1);
s_core.halt = rvfi_q[i].halt;
s_core.intr = rvfi_q[i].intr;
s_core.mode = rvfi_q[i].mode;
s_core.ixl = rvfi_q[i].ixl;
s_core.rs1_addr = rvfi_q[i].rs1_addr;
s_core.rs2_addr = rvfi_q[i].rs2_addr;
s_core.rs1_rdata = rvfi_q[i].rs1_rdata;
s_core.rs2_rdata = rvfi_q[i].rs2_rdata;
s_core.rd1_addr = rvfi_q[i].rd_addr;
s_core.rd1_wdata = rvfi_q[i].rd_wdata;
s_core.pc_rdata = rvfi_q[i].pc_rdata;
s_core.pc_wdata = rvfi_q[i].pc_wdata;
s_core.mem_addr = rvfi_q[i].mem_addr;
s_core.mem_rmask = rvfi_q[i].mem_rmask;
s_core.mem_wmask = rvfi_q[i].mem_wmask;
s_core.mem_rdata = rvfi_q[i].mem_rdata;
s_core.mem_wdata = rvfi_q[i].mem_wdata;

`define GET_RVFI_CSR(CSR_ADDR, CSR_NAME, CSR_INDEX) \
s_core.csr_valid[CSR_INDEX] = 1; \
s_core.csr_addr [CSR_INDEX] = CSR_ADDR;\
s_core.csr_rdata[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.rdata;\
s_core.csr_rmask[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.rmask;\
s_core.csr_wdata[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wdata;\
s_core.csr_wmask[CSR_INDEX] = rvfi_csr_i.``CSR_NAME``.wmask;

if (rvfi_i[i].valid || rvfi_i[i].trap) begin
s_core.order = rvfi_i[i].order;
s_core.insn = rvfi_i[i].insn;
s_core.trap = rvfi_i[i].trap;
s_core.cause = rvfi_i[i].cause;
s_core.halt = rvfi_i[i].halt;
s_core.intr = rvfi_i[i].intr;
s_core.mode = rvfi_i[i].mode;
s_core.ixl = rvfi_i[i].ixl;
s_core.rs1_addr = rvfi_i[i].rs1_addr;
s_core.rs2_addr = rvfi_i[i].rs2_addr;
s_core.rs1_rdata = rvfi_i[i].rs1_rdata;
s_core.rs2_rdata = rvfi_i[i].rs2_rdata;
s_core.rd1_addr = rvfi_i[i].rd_addr;
s_core.rd1_wdata = rvfi_i[i].rd_wdata;
s_core.pc_rdata = rvfi_i[i].pc_rdata;
s_core.pc_wdata = rvfi_i[i].pc_wdata;
s_core.mem_addr = rvfi_i[i].mem_addr;
s_core.mem_rmask = rvfi_i[i].mem_rmask;
s_core.mem_wmask = rvfi_i[i].mem_wmask;
s_core.mem_rdata = rvfi_i[i].mem_rdata;
s_core.mem_wdata = rvfi_i[i].mem_wdata;
`GET_RVFI_CSR (CSR_MSTATUS , mstatus , 0)
`GET_RVFI_CSR (CSR_MCAUSE , mcause , 1)
`GET_RVFI_CSR (CSR_MEPC , mepc , 2)
`GET_RVFI_CSR (CSR_MTVEC , mtvec , 3)
`GET_RVFI_CSR (CSR_MISA , misa , 4)
`GET_RVFI_CSR (CSR_MTVAL , mtval , 5)
`GET_RVFI_CSR (CSR_MIDELEG , mideleg , 6)
`GET_RVFI_CSR (CSR_MEDELEG , medeleg , 7)
`GET_RVFI_CSR (CSR_SATP , satp , 8)
`GET_RVFI_CSR (CSR_MIE , mie , 9)
`GET_RVFI_CSR (CSR_STVEC , stvec ,10)
`GET_RVFI_CSR (CSR_SSCRATCH , sscratch ,11)
`GET_RVFI_CSR (CSR_SEPC , sepc ,12)
`GET_RVFI_CSR (CSR_MSCRATCH , mscratch ,13)
`GET_RVFI_CSR (CSR_STVAL , stval ,14)
`GET_RVFI_CSR (CSR_SCAUSE , scause ,15)
`GET_RVFI_CSR (CSR_PMPADDR0 , pmpaddr[0] ,16)
`GET_RVFI_CSR (CSR_PMPCFG0 , pmpcfg0 ,17)

rvfi_spike_step(s_core, s_reference_model);
rvfi_compare(s_core, s_reference_model);
Expand Down
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