add target stage registers

src/main/scala/hwdbg/configs/configs.scala

@@ -65,6 +65,11 @@ object DebuggerConfigurations {
   // Data width of the Block RAM (BRAM)
   //
   val BLOCK_RAM_DATA_WIDTH: Int = 32
+
+  //
+  // Single stage script symbol size (equal to sizeof(SYMBOL))
+  //
+  val SINGLE_STAGE_SCRIPT_SYMBOL_SIZE: Int = 32
 }
 
 /**

src/main/scala/hwdbg/main.scala

@@ -92,6 +92,22 @@ class DebuggerMain(
   val receivingData = Wire(UInt(bramDataWidth.W))
   val sendWaitForBuffer = Wire(Bool())
 
+  // -----------------------------------------------------------------------
+  // Create instance from script execution engine
+  //
+  val (outputPin) =
+    ScriptExecutionEngine(
+      debug,
+      numberOfPins,
+      maximumNumberOfStages,
+      bramAddrWidth,
+      bramDataWidth,
+      portsConfiguration
+    )(
+      io.en,
+      io.inputPin
+    )
+
   // -----------------------------------------------------------------------
   // Create instance from interpreter
   //
@@ -157,22 +173,6 @@ class DebuggerMain(
   receivingData := outReceivingData
   sendWaitForBuffer := outSendWaitForBuffer
 
-  // -----------------------------------------------------------------------
-  // Create instance from script execution engine
-  //
-  val (outputPin) =
-    ScriptExecutionEngine(
-      debug,
-      numberOfPins,
-      maximumNumberOfStages,
-      bramAddrWidth,
-      bramDataWidth,
-      portsConfiguration
-    )(
-      io.en,
-      io.inputPin
-    )
-
   // -----------------------------------------------------------------------
   // Configure the output signals
   //

src/main/scala/hwdbg/script/exec.scala

@@ -68,10 +68,16 @@ class ScriptExecutionEngine(
       //
       stageRegs.pinValues(i) := io.inputPin.asUInt
 
+      //
+      // Each pin start initially start from 0th target stage
+      //
+      // stageRegs.targetStage(i) := 0.U
+
     } else if (i == (maximumNumberOfStages - 1)) {
 
       //
       // At the last stage, the state registers should be passed to the output
+      // Note: At this stage script symbol is useless
       //
       for (j <- 0 until numberOfPins) {
         outputPin(j) := stageRegs.pinValues(i)(j)
@@ -84,6 +90,12 @@ class ScriptExecutionEngine(
       // the next level of stage registers
       //
       stageRegs.pinValues(i + 1) := stageRegs.pinValues(i)
+
+      //
+      // Pass the target stage symbol number to the next stage
+      //
+      // stageRegs.targetStage(i + 1) := stageRegs.targetStage(i) // Uncomment
+
     }
   }
 

src/main/scala/hwdbg/types/stage.scala

@@ -16,13 +16,19 @@
 package hwdbg.stage
 
 import chisel3._
+import chisel3.util.log2Ceil
 
 import hwdbg.configs._
 
 class StageRegisters(
     debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
     numberOfPins: Int = DebuggerConfigurations.NUMBER_OF_PINS,
-    maximumNumberOfStages: Int = DebuggerConfigurations.MAXIMUM_NUMBER_OF_STAGES
+    maximumNumberOfStages: Int = DebuggerConfigurations.MAXIMUM_NUMBER_OF_STAGES,
+    singleStageScriptSymbolSize: Int = DebuggerConfigurations.SINGLE_STAGE_SCRIPT_SYMBOL_SIZE
 ) extends Bundle {
-  val pinValues = Vec(maximumNumberOfStages, UInt(numberOfPins.W))
+  val pinValues = Vec(maximumNumberOfStages, UInt(numberOfPins.W)) // The value of each pin in each stage (should be passed to the next stage)
+  val scriptSymbol = UInt(singleStageScriptSymbolSize.W) // Interpreted script symbol for the target stage (should NOT be passed to the next stage)
+  val targetStage = UInt(
+    log2Ceil(maximumNumberOfStages).W
+  ) // Target stage that needs to be executed for the current pin values (should be passed to the next stage)
 }