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Change await RisingEdge to Timer
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@SinaKarvandi
SinaKarvandi committed May 6, 2024
1 parent 44a0631 commit 68cd5a1
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89 changes: 44 additions & 45 deletions sim/hwdbg/DebuggerModuleTestingBRAM/test_DebuggerModuleTestingBRAM.py
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge, Timer
from cocotb.triggers import Timer
from cocotb.types import LogicArray

maximum_number_of_clock_cycles = 1000
Expand Down Expand Up @@ -231,43 +231,43 @@ async def DebuggerModuleTestingBRAM_test(dut):
#
# Assert initial output is unknown
#
# assert LogicArray(dut.io_outputPin_0.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_1.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_2.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_3.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_4.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_5.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_6.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_7.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_8.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_9.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_10.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_11.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_12.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_13.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_14.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_15.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_16.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_17.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_18.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_19.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_20.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_21.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_22.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_23.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_24.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_25.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_26.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_27.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_28.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_29.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_30.value) == LogicArray("Z")
# assert LogicArray(dut.io_outputPin_31.value) == LogicArray("Z")

#
# Create a 1ns period clock on port clock
#
clock = Clock(dut.clock, 1, units="ns")
assert LogicArray(dut.io_outputPin_0.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_1.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_2.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_3.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_4.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_5.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_6.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_7.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_8.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_9.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_10.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_11.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_12.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_13.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_14.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_15.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_16.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_17.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_18.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_19.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_20.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_21.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_22.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_23.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_24.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_25.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_26.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_27.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_28.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_29.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_30.value) == LogicArray("Z")
assert LogicArray(dut.io_outputPin_31.value) == LogicArray("Z")

#
# Create a 10ns period clock on port clock
#
clock = Clock(dut.clock, 10, units="ns")

#
# Start the clock. Start it low to avoid issues on the first RisingEdge
Expand All @@ -287,8 +287,7 @@ async def DebuggerModuleTestingBRAM_test(dut):
#
dut.reset.value = 1
for _ in range(10):
# await RisingEdge(dut.clock)
await Timer(1, units="ns")
await Timer(10, units="ns")
dut.reset.value = 0

dut._log.info("Enabling an interrupting chip to receive commands from BRAM")
Expand Down Expand Up @@ -338,13 +337,13 @@ async def DebuggerModuleTestingBRAM_test(dut):
# Tell the hwdbg to receive BRAM results
#
dut.io_plInSignal.value = 1
await Timer(1, units="ns")
await Timer(10, units="ns")
dut.io_plInSignal.value = 0

#
# Synchronize with the clock. This will regisiter the initial `inputPinX` value
#
await Timer(1, units="ns")
await Timer(10, units="ns")

#
# Wait until the debuggee sends an interrupt to debugger
Expand All @@ -360,7 +359,7 @@ async def DebuggerModuleTestingBRAM_test(dut):
print("Number of clock cycles spent in debuggee (PL): " + str(clock_counter))

clock_counter = clock_counter + 1
await Timer(1, units="ns")
await Timer(10, units="ns")

#
# Apply a limitation to the number of clock cycles that
Expand All @@ -382,7 +381,7 @@ async def DebuggerModuleTestingBRAM_test(dut):
#
# Run one more clock cycle to apply the latest BRAM modifications
#
await Timer(1, units="ns")
await Timer(10, units="ns")

#
# Print contents of BRAM
Expand All @@ -394,4 +393,4 @@ async def DebuggerModuleTestingBRAM_test(dut):
# of more clock cycles
#
for _ in range(10):
await Timer(1, units="ns")
await Timer(10, units="ns")
16 changes: 8 additions & 8 deletions sim/hwdbg/communication/DebuggerPacketReceiver/test_DebuggerPacketReceiver.py
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Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.triggers import Timer
from cocotb.types import LogicArray

'''
Expand Down Expand Up @@ -73,7 +73,7 @@ async def DebuggerPacketReceiver_test(dut):
#
dut.reset.value = 1
for _ in range(10):
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.reset.value = 0

dut._log.info("Enabling chip")
Expand All @@ -92,7 +92,7 @@ async def DebuggerPacketReceiver_test(dut):
# a rising-edge detector, so we'll need to make it low)
#
dut.io_plInSignal.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_plInSignal.value = 0

#
Expand Down Expand Up @@ -152,7 +152,7 @@ async def DebuggerPacketReceiver_test(dut):
#
if test_number % 3 == 0:
dut.io_noNewDataReceiver.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_noNewDataReceiver.value = 0
else:
#
Expand All @@ -168,20 +168,20 @@ async def DebuggerPacketReceiver_test(dut):
#
# Go to the next clock cycle
#
await RisingEdge(dut.clock)
await Timer(10, units="ns")

if test_number % 3 != 0:
dut.io_noNewDataReceiver.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_noNewDataReceiver.value = 0

#
# Run extra waiting clocks
#
for _ in range(10):
await RisingEdge(dut.clock)
await Timer(10, units="ns")

#
# Check the final input on the next clock
#
await RisingEdge(dut.clock)
await Timer(10, units="ns")
18 changes: 9 additions & 9 deletions sim/hwdbg/communication/DebuggerPacketSender/test_DebuggerPacketSender.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.triggers import Timer
from cocotb.types import LogicArray

'''
Expand Down Expand Up @@ -72,7 +72,7 @@ async def DebuggerPacketSender_test(dut):
#
dut.reset.value = 1
for _ in range(10):
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.reset.value = 0

dut._log.info("Enabling chip")
Expand All @@ -96,7 +96,7 @@ async def DebuggerPacketSender_test(dut):
# a rising-edge detector, so we'll need to make it low)
#
dut.io_beginSendingBuffer.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_beginSendingBuffer.value = 0

#
Expand All @@ -113,7 +113,7 @@ async def DebuggerPacketSender_test(dut):
#
# Synchronize with the clock. This will apply the initial values
#
await RisingEdge(dut.clock)
await Timer(10, units="ns")

#
# This will change the behavior of the data producer to only
Expand All @@ -138,28 +138,28 @@ async def DebuggerPacketSender_test(dut):
#
dut.io_sendingData.value = val

await RisingEdge(dut.clock)
await Timer(10, units="ns")

#
# Now, tell the sender module that there is no longer needed to send data
#
for i in range(100):
if dut.io_sendWaitForBuffer.value == 1:
dut.io_noNewDataSender.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_noNewDataSender.value = 0
break

await RisingEdge(dut.clock)
await Timer(10, units="ns")


#
# Run extra waiting clocks
#
for _ in range(10):
await RisingEdge(dut.clock)
await Timer(10, units="ns")

#
# Check the final input on the next clock
#
await RisingEdge(dut.clock)
await Timer(10, units="ns")
32 changes: 16 additions & 16 deletions sim/hwdbg/communication/SendReceiveSynchronizer/test_SendReceiveSynchronizer.py
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@

import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
from cocotb.triggers import Timer
from cocotb.types import LogicArray

'''
Expand Down Expand Up @@ -91,7 +91,7 @@ async def SendReceiveSynchronizer_test(dut):
#
dut.reset.value = 1
for _ in range(10):
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.reset.value = 0

dut._log.info("Enabling chip")
Expand All @@ -116,14 +116,14 @@ async def SendReceiveSynchronizer_test(dut):
# a rising-edge detector, so we'll need to make it low)
#
dut.io_plInSignal.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_plInSignal.value = 0

#
# Activate sending logic to test whether the chip fails synchronizing signals or not
#
dut.io_beginSendingBuffer.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_beginSendingBuffer.value = 0

#
Expand Down Expand Up @@ -228,7 +228,7 @@ async def SendReceiveSynchronizer_test(dut):
#
if test_number % 3 == 0:
dut.io_noNewDataReceiver.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_noNewDataReceiver.value = 0
else:
#
Expand All @@ -243,19 +243,19 @@ async def SendReceiveSynchronizer_test(dut):
#
# Go to the next clock cycle
#
await RisingEdge(dut.clock)
await Timer(10, units="ns")


if test_number % 3 != 0:
dut.io_noNewDataReceiver.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_noNewDataReceiver.value = 0

#
# Run extra waiting clocks
#
for _ in range(10):
await RisingEdge(dut.clock)
await Timer(10, units="ns")

###############################################################
# #
Expand All @@ -276,14 +276,14 @@ async def SendReceiveSynchronizer_test(dut):
# a rising-edge detector, so we'll need to make it low)
#
dut.io_beginSendingBuffer.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_beginSendingBuffer.value = 0

#
# Activate receiving logic to test whether the chip fails synchronizing signals or not
#
dut.io_plInSignal.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_plInSignal.value = 0

#
Expand All @@ -300,7 +300,7 @@ async def SendReceiveSynchronizer_test(dut):
#
# Synchronize with the clock. This will apply the initial values
#
await RisingEdge(dut.clock)
await Timer(10, units="ns")

#
# This will change the behavior of the data producer to only
Expand All @@ -325,28 +325,28 @@ async def SendReceiveSynchronizer_test(dut):
#
dut.io_sendingData.value = val

await RisingEdge(dut.clock)
await Timer(10, units="ns")

#
# Now, tell the sender module that there is no longer needed to send data
#
for i in range(100):
if dut.io_sendWaitForBuffer.value == 1:
dut.io_noNewDataSender.value = 1
await RisingEdge(dut.clock)
await Timer(10, units="ns")
dut.io_noNewDataSender.value = 0
break

await RisingEdge(dut.clock)
await Timer(10, units="ns")


#
# Run extra waiting clocks
#
for _ in range(10):
await RisingEdge(dut.clock)
await Timer(10, units="ns")

#
# Check the final input on the next clock
#
await RisingEdge(dut.clock)
await Timer(10, units="ns")

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