update scala doc style

HyperDbg · Apr 16, 2024 · 3b53e6f · 3b53e6f
1 parent f391a5a
commit 3b53e6f
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Showing 13 changed files with 261 additions and 271 deletions.
diff --git a/.scalafmt.conf b/.scalafmt.conf
@@ -1,2 +1,5 @@
 version = "3.8.1"
-runner.dialect = scala213
+runner.dialect = scala213
+maxColumn = 150
+docstrings.style = Asterisk
+docstrings.oneline = unfold
diff --git a/src/main/scala/hwdbg/communication/interpreter.scala b/src/main/scala/hwdbg/communication/interpreter.scala
@@ -1,17 +1,18 @@
-/** @file
-  *   interpreter.scala
-  * @author
-  *   Sina Karvandi ([email protected])
-  * @brief
-  *   Remote debugger packet interpreter module
-  * @details
-  * @version 0.1
-  * @date
-  *   2024-04-08
-  *
-  * @copyright
-  *   This project is released under the GNU Public License v3.
-  */
+/**
+ * @file
+ *   interpreter.scala
+ * @author
+ *   Sina Karvandi ([email protected])
+ * @brief
+ *   Remote debugger packet interpreter module
+ * @details
+ * @version 0.1
+ * @date
+ *   2024-04-08
+ *
+ * @copyright
+ *   This project is released under the GNU Public License v3.
+ */
 package hwdbg.communication
 
 import chisel3._
@@ -25,8 +26,7 @@ import hwdbg.constants._
 
 object DebuggerPacketInterpreterEnums {
   object State extends ChiselEnum {
-    val sIdle, sInit, sReadChecksum, sReadIndicator, sReadTypeOfThePacket,
-        sReadRequestedActionOfThePacket, sDone = Value
+    val sIdle, sInit, sReadChecksum, sReadIndicator, sReadTypeOfThePacket, sReadRequestedActionOfThePacket, sDone = Value
   }
 }
 
@@ -67,9 +67,7 @@ class DebuggerPacketInterpreter(
     //
     val interpretationDone = Output(Bool()) // interpretation done or not?
     val foundValidPacket = Output(Bool()) // packet was valid or not
-    val requestedActionOfThePacket = Output(
-      UInt(new DebuggerRemotePacket().getWidth.W)
-    ) // the requested action
+    val requestedActionOfThePacket = Output(UInt(new DebuggerRemotePacket().getWidth.W)) // the requested action
 
   })
 
@@ -93,9 +91,7 @@ class DebuggerPacketInterpreter(
   //
   // Structure (as register) of the received packet buffer
   //
-  val regReceivedPacketBuffer = RegInit(
-    0.U.asTypeOf(new DebuggerRemotePacket())
-  )
+  val regReceivedPacketBuffer = RegInit(0.U.asTypeOf(new DebuggerRemotePacket()))
 
   //
   // Apply the chip enable signal
@@ -109,18 +105,10 @@ class DebuggerPacketInterpreter(
         //
         // Create logs from communication structure offsets
         //
-        LogInfo(debug)(
-          f"The offset of Checksum is 0x${regReceivedPacketBuffer.Offset.checksum}%x"
-        )
-        LogInfo(debug)(
-          f"The offset of Indicator is 0x${regReceivedPacketBuffer.Offset.indicator}%x"
-        )
-        LogInfo(debug)(
-          f"The offset of TypeOfThePacket is 0x${regReceivedPacketBuffer.Offset.typeOfThePacket}%x"
-        )
-        LogInfo(debug)(
-          f"The offset of RequestedActionOfThePacket is 0x${regReceivedPacketBuffer.Offset.requestedActionOfThePacket}%x"
-        )
+        LogInfo(debug)(f"The offset of Checksum is 0x${regReceivedPacketBuffer.Offset.checksum}%x")
+        LogInfo(debug)(f"The offset of Indicator is 0x${regReceivedPacketBuffer.Offset.indicator}%x")
+        LogInfo(debug)(f"The offset of TypeOfThePacket is 0x${regReceivedPacketBuffer.Offset.typeOfThePacket}%x")
+        LogInfo(debug)(f"The offset of RequestedActionOfThePacket is 0x${regReceivedPacketBuffer.Offset.requestedActionOfThePacket}%x")
 
         //
         // Check whether the interrupt from the PS is received or not
@@ -200,15 +188,14 @@ class DebuggerPacketInterpreter(
         //
         // Check whether the indicator is valid or not
         //
-        when(
-          regReceivedPacketBuffer.Indicator === HyperDbgSharedConstants.INDICATOR_OF_HYPERDBG_PACKET.U
-        ) {
+        when(regReceivedPacketBuffer.Indicator === HyperDbgSharedConstants.INDICATOR_OF_HYPERDBG_PACKET.U) {
 
           //
           // Indicator of packet is valid
           // (Goes to the next section)
           //
           state := sReadRequestedActionOfThePacket
+
         }.otherwise {
 
           //
@@ -219,7 +206,6 @@ class DebuggerPacketInterpreter(
           regInterpretationDone := true.B
           state := sIdle
         }
-
       }
       is(sReadRequestedActionOfThePacket) {
 
@@ -231,9 +217,7 @@ class DebuggerPacketInterpreter(
         //
         // Check whether the type of the packet is valid or not
         //
-        when(
-          regReceivedPacketBuffer.Indicator === HyperDbgSharedConstants.INDICATOR_OF_HYPERDBG_PACKET.U
-        ) {
+        when(regReceivedPacketBuffer.Indicator === HyperDbgSharedConstants.INDICATOR_OF_HYPERDBG_PACKET.U) {
 
           //
           // Type of packet is valid
@@ -329,11 +313,6 @@ object DebuggerPacketInterpreter {
     //
     // Return the output result
     //
-    (
-      rdWrAddr,
-      interpretationDone,
-      foundValidPacket,
-      requestedActionOfThePacket
-    )
+    (rdWrAddr, interpretationDone, foundValidPacket, requestedActionOfThePacket)
   }
 }
diff --git a/src/main/scala/hwdbg/communication/sender.scala b/src/main/scala/hwdbg/communication/sender.scala
@@ -1,17 +1,18 @@
-/** @file
-  *   sender.scala
-  * @author
-  *   Sina Karvandi ([email protected])
-  * @brief
-  *   Remote debugger packet sender module
-  * @details
-  * @version 0.1
-  * @date
-  *   2024-04-16
-  *
-  * @copyright
-  *   This project is released under the GNU Public License v3.
-  */
+/**
+ * @file
+ *   sender.scala
+ * @author
+ *   Sina Karvandi ([email protected])
+ * @brief
+ *   Remote debugger packet sender module
+ * @details
+ * @version 0.1
+ * @date
+ *   2024-04-16
+ *
+ * @copyright
+ *   This project is released under the GNU Public License v3.
+ */
 package hwdbg.communication
 
 import chisel3._
@@ -32,7 +33,8 @@ object DebuggerPacketSenderEnums {
 class DebuggerPacketSender(
     debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG,
     bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH,
-    bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH
+    bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH,
+    lengthOfDataSendingArray: Int = DebuggerConfigurations.LENGTH_OF_DATA_SENDING_ARRAY
 ) extends Module {
 
   //
@@ -65,12 +67,10 @@ class DebuggerPacketSender(
     //
     // Sending signals
     //
+    val beginSendingBuffer = Input(Bool()) // should sender start sending buffers or not?
     val sendingSignalDone = Output(Bool()) // sending signal done or not?
-    val foundValidPacket = Output(Bool()) // packet was valid or not
-    val requestedActionOfThePacket =
-      Output(
-        UInt(new DebuggerRemotePacket().getWidth.W)
-      ) // the requested action
+    val requestedActionOfThePacket = Output(UInt(new DebuggerRemotePacket().getWidth.W)) // the requested action
+    val sendingDataArray = Input(Vec(lengthOfDataSendingArray, UInt((bramDataWidth.W)))) // data to be sent to the debugger
 
   })
 

diff --git a/src/main/scala/hwdbg/configs/configs.scala b/src/main/scala/hwdbg/configs/configs.scala
@@ -1,25 +1,27 @@
-/** @file
-  *   configs.scala
-  * @author
-  *   Sina Karvandi ([email protected])
-  * @brief
-  *   Configuration files
-  * @details
-  * @version 0.1
-  * @date
-  *   2024-04-03
-  *
-  * @copyright
-  *   This project is released under the GNU Public License v3.
-  */
+/**
+ * @file
+ *   configs.scala
+ * @author
+ *   Sina Karvandi ([email protected])
+ * @brief
+ *   Configuration files
+ * @details
+ * @version 0.1
+ * @date
+ *   2024-04-03
+ *
+ * @copyright
+ *   This project is released under the GNU Public License v3.
+ */
 package hwdbg.configs
 
 import chisel3._
 import chisel3.util._
 
-/** @brief
-  *   The configuration of ports and pins
-  */
+/**
+ * @brief
+ *   The configuration of ports and pins
+ */
 object DebuggerPorts {
 
   //
@@ -40,14 +42,14 @@ object DebuggerPorts {
   //                port 1 (out) -> contains 9 pins
   //                port 2 (out) -> contains 11 pins
   //
-  val PORT_PINS_MAP_OUTPUT: Map[Int, Int] =
-    Map(0 -> 4, 1 -> 7, 2 -> 11, 3 -> 10)
+  val PORT_PINS_MAP_OUTPUT: Map[Int, Int] = Map(0 -> 4, 1 -> 7, 2 -> 11, 3 -> 10)
 
 }
 
-/** @brief
-  *   Design constants
-  */
+/**
+ * @brief
+ *   Design constants
+ */
 object DebuggerConfigurations {
 
   //
@@ -75,11 +77,17 @@ object DebuggerConfigurations {
   //
   val BLOCK_RAM_DATA_WIDTH: Int = 32
 
+  //
+  // Maximum number of data to send to the debuggee
+  //
+  val LENGTH_OF_DATA_SENDING_ARRAY: Int = 4
+
 }
 
-/** @brief
-  *   The constants for configuration
-  */
+/**
+ * @brief
+ *   The constants for configuration
+ */
 object GeneralConfigurations {
 
   //

diff --git a/src/main/scala/hwdbg/configs/constants.scala b/src/main/scala/hwdbg/configs/constants.scala
@@ -1,42 +1,44 @@
-/** @file
-  *   constants.scala
-  * @author
-  *   Sina Karvandi ([email protected])
-  * @brief
-  *   Constant values
-  * @details
-  * @version 0.1
-  * @date
-  *   2024-04-16
-  *
-  * @copyright
-  *   This project is released under the GNU Public License v3.
-  */
+/**
+ * @file
+ *   constants.scala
+ * @author
+ *   Sina Karvandi ([email protected])
+ * @brief
+ *   Constant values
+ * @details
+ * @version 0.1
+ * @date
+ *   2024-04-16
+ *
+ * @copyright
+ *   This project is released under the GNU Public License v3.
+ */
 package hwdbg.constants
 
 import chisel3._
 import chisel3.util._
 
-/** @brief
-  *   Shared value with HyperDbg
-  * @warning
-  *   used in HyperDbg
-  */
+/**
+ * @brief
+ *   Shared value with HyperDbg
+ * @warning
+ *   used in HyperDbg
+ */
 object HyperDbgSharedConstants {
 
   //
   // Constant indicator of a HyperDbg packet
   //
-  val INDICATOR_OF_HYPERDBG_PACKET: Long =
-    0x4859504552444247L // HYPERDBG = 0x4859504552444247
+  val INDICATOR_OF_HYPERDBG_PACKET: Long = 0x4859504552444247L // HYPERDBG = 0x4859504552444247
 
 }
 
-/** @brief
-  *   Enumeration for different packet types in HyperDbg packets
-  * @warning
-  *   Used in HyperDbg
-  */
+/**
+ * @brief
+ *   Enumeration for different packet types in HyperDbg packets
+ * @warning
+ *   Used in HyperDbg
+ */
 object DEBUGGER_REMOTE_PACKET_TYPE extends Enumeration {
 
   //