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set dynamic size for the requested packet type
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/** @file | ||
* sender.scala | ||
* @author | ||
* Sina Karvandi ([email protected]) | ||
* @brief | ||
* Remote debugger packet sender module | ||
* @details | ||
* @version 0.1 | ||
* @date | ||
* 2024-04-16 | ||
* | ||
* @copyright | ||
* This project is released under the GNU Public License v3. | ||
*/ | ||
package hwdbg.communication | ||
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import chisel3._ | ||
import chisel3.util.{switch, is} | ||
import circt.stage.ChiselStage | ||
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import hwdbg.configs._ | ||
import hwdbg.types._ | ||
import hwdbg.utils._ | ||
import hwdbg.constants._ | ||
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object DebuggerPacketSenderEnums { | ||
object State extends ChiselEnum { | ||
val sIdle, sInit, sDone = Value | ||
} | ||
} | ||
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class DebuggerPacketSender( | ||
debug: Boolean = DebuggerConfigurations.ENABLE_DEBUG, | ||
bramAddrWidth: Int = DebuggerConfigurations.BLOCK_RAM_ADDR_WIDTH, | ||
bramDataWidth: Int = DebuggerConfigurations.BLOCK_RAM_DATA_WIDTH | ||
) extends Module { | ||
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// | ||
// Import state enum | ||
// | ||
import DebuggerPacketSenderEnums.State | ||
import DebuggerPacketSenderEnums.State._ | ||
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val io = IO(new Bundle { | ||
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// | ||
// Chip signals | ||
// | ||
val en = Input(Bool()) // chip enable signal | ||
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// | ||
// Interrupt signals (lines) | ||
// Note: Only PS output signal is exported here, | ||
// a separate module will control the PL signal | ||
// | ||
val psOutInterrupt = Output(Bool()) // PL to PS interrupt | ||
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// | ||
// BRAM (Block RAM) ports | ||
// | ||
val rdWrAddr = Output(UInt(bramAddrWidth.W)) // read/write address | ||
val wrEna = Output(Bool()) // enable writing | ||
val wrData = Output(UInt(bramDataWidth.W)) // write data | ||
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// | ||
// Sending signals | ||
// | ||
val sendingSignalDone = Output(Bool()) // sending signal done or not? | ||
val foundValidPacket = Output(Bool()) // packet was valid or not | ||
val requestedActionOfThePacket = | ||
Output( | ||
UInt(new DebuggerRemotePacket().getWidth.W) | ||
) // the requested action | ||
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}) | ||
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} |
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