[test] Add riscv_compliance patch

- Add opentitan target - Remove tests that are known to fail. These should be restored later. Signed-off-by: Timothy Chen <[email protected]>
GregAC · Dec 2, 2019 · 82efee9 · 82efee9
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diff --git a/.../patches/riscv_compliance/0001-test-Add-OpenTitan-target-to-riscv-compliance-testin.patch b/.../patches/riscv_compliance/0001-test-Add-OpenTitan-target-to-riscv-compliance-testin.patch
diff --git a/sw/vendor/patches/riscv_compliance/0002-Remove-specific-tests-that-do-not-pass-on-ibex.patch b/sw/vendor/patches/riscv_compliance/0002-Remove-specific-tests-that-do-not-pass-on-ibex.patch
diff --git a/sw/vendor/riscv_compliance.vendor.hjson b/sw/vendor/riscv_compliance.vendor.hjson
@@ -4,6 +4,7 @@
 {
   name: "riscv_compliance",
   target_dir: "riscv_compliance",
+  patch_dir: "patches/riscv_compliance",
 
   upstream: {
     url: "https://github.com/riscv/riscv-compliance.git",
@@ -13,8 +14,17 @@
   exclude_from_upstream: [
     "doc",
     "spec",
-    "riscv-target",
     "riscv-ovpsim",
+    "riscv-target/Codasip-simulator",
+    "riscv-target/grift",
+    "riscv-target/ibex",
+    "riscv-target/ri5cy",
+    "riscv-target/riscvOVPsim",
+    "riscv-target/rocket",
+    "riscv-target/sail-riscv-c",
+    "riscv-target/sail-riscv-ocaml",
+    "riscv-target/sifive-formal",
+    "riscv-target/spike",
     "riscv-test-suite/rv32mi",
     "riscv-test-suite/rv32si",
     "riscv-test-suite/rv32ua",

diff --git a/sw/vendor/riscv_compliance/riscv-target/README.md b/sw/vendor/riscv_compliance/riscv-target/README.md
@@ -0,0 +1,5 @@
+# RISC-V Targets
+
+The Target Environment needs setting up to allow the compliance tests to be run on that Target. This can be used while developing compliance test suites or it can be used with new Targets to see if they correctly execute the compliance test suites and are compliant!
+
+This directory provides the necsessary files for the currently available Targets.
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md b/sw/vendor/riscv_compliance/riscv-target/opentitan/README.md
@@ -0,0 +1,97 @@
+
+# Overview
+The RISC-V compliance test can be run on either OpenTitan FPGA or Verilator.
+OpenTitan is an open source project to build transparent, high-quality reference designs for silicon root of trust chips.
+Please see the [OpenTitan website](https://opentitan.org) for more details.
+
+To run on Verilator, set the variables below
+
+```console
+$ export RISCV_TARGET=opentitan
+$ export RISCV_DEVICE=rv32imc
+$ export OPENTITAN_TARGET=verilator
+```
+
+To run on FPGA, set the variables below.
+The `FPGA_UART` variable must be set to wherever a valid device is connected.
+
+```console
+$ export RISCV_TARGET=opentitan
+$ export RISCV_DEVICE=rv32imc
+$ export OT_TARGET=fpga
+$ export OT_FPGA_UART=/dev/tty*
+```
+
+By default, the test assumes there exists a valid Verilator build at `${REPO_TOP}/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator`.
+If your Verilator build is at a different location, please set that as well when running with Verilator.
+
+```console
+$ export TARGET_SIM=${PATH_TO_VERILATOR_BUILD}
+```
+
+When running against FPGA, the test assumes the FPGA is already programmed and ready to go.
+To quickly get started with a verilator binary or FPGA bitfile, please see the [OpenTitan quick start guide](https://docs.opentitan.org/doc/ug/quickstart/)
+
+
+Now, run the tests from the riscv_compliance directory.
+The following output will be seen (software build steps are truncated).
+The example below uses Verilator as an example, but the FPGA output is nearly identical.
+
+```console
+$ cd $RISCV_COMPLIANCE_REPO_BASE
+$ make RISCV_ISA=rv32i \
+  && make RISCV_ISA=rv32im \
+  && make RISCV_ISA=rv32imc
+
+
+Rom initialized with program at $REPO_TOP/sw/vendor/riscv_compliance/../../boot_rom/rom.vmem
+
+Flash initialized with program at $REPO_TOP/sw/vendor/riscv_compliance/work/rv32i/I-ENDIANESS-01.elf.vmem
+
+JTAG: Virtual JTAG interface jtag0 is listening on port 44853. Use
+OpenOCD and the following configuration to connect:
+  interface remote_bitbang
+  remote_bitbang_host localhost
+  remote_bitbang_port 44853
+
+SPI: Created /dev/pts/21 for spi0. Connect to it with any terminal program, e.g.
+$ screen /dev/pts/21
+NOTE: a SPI transaction is run for every 4 characters entered.
+SPI: Monitor output file created at $REPO_TOP/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/spi0.log. Works well with tail:
+$ tail -f $REPO_TOP/sw/vendor/riscv_compliance/riscv-test-suite/rv32i/spi0.log
+
+UART: Created /dev/pts/22 for uart0. Connect to it with any terminal program, e.g.
+$ screen /dev/pts/22
+
+Simulation running, end by pressing CTRL-c.
+TOP.top_earlgrey_verilator.top_earlgrey.core.ibex_tracer_i: Writing execution trace to trace_core_00000000.log
+Verilator sim termination requested
+Your simulation wrote to 0x10008000
+
+...
+
+Compare to reference files ...
+
+Check         I-ADD-01 ... OK
+Check        I-ADDI-01 ... OK
+Check         I-AND-01 ... OK
+Check        I-ANDI-01 ... OK
+
+...
+
+--------------------------------
+OK: 55/55
+
+
+```
+
+
+## Removed Tests
+A small number of tests are not run for OpenTitan riscv_compliance since the underlying core does not yet support specific features.
+The removed tests are the following:
+
+* I-MISALIGN_JMP-01
+* I-MISALIGN_LDST-01
+* I-FENCE.I-01
+* I-ECALL-01
+* I-EBREAK-01
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_io.h b/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_io.h
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// RISC-V Compliance IO Test Header File
+
+
+#ifndef _COMPLIANCE_IO_H
+#define _COMPLIANCE_IO_H
+
+//-----------------------------------------------------------------------
+// RV IO Macros (Non functional)
+//-----------------------------------------------------------------------
+
+#define RVTEST_IO_INIT
+#define RVTEST_IO_WRITE_STR(_SP, _STR)
+#define RVTEST_IO_CHECK()
+#define RVTEST_IO_ASSERT_GPR_EQ(_SP, _R, _I)
+#define RVTEST_IO_ASSERT_SFPR_EQ(_F, _R, _I)
+#define RVTEST_IO_ASSERT_DFPR_EQ(_D, _R, _I)
+
+#endif // _COMPLIANCE_IO_H
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h b/sw/vendor/riscv_compliance/riscv-target/opentitan/compliance_test.h
@@ -0,0 +1,39 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+// RISC-V Compliance Test Header File
+
+#ifndef _COMPLIANCE_TEST_H
+#define _COMPLIANCE_TEST_H
+
+#include "riscv_test.h"
+
+//-----------------------------------------------------------------------
+// RV Compliance Macros
+//-----------------------------------------------------------------------
+#define RV_COMPLIANCE_HALT                                                    \
+        la sp, _stack_start;                                                  \
+        j dump_signature;                                                     \
+      loop_forever:                                                           \
+        wfi;                                                                  \
+        j loop_forever;                                                       \
+
+#define RV_COMPLIANCE_RV32M                                                   \
+        RVTEST_RV32M                                                          \
+
+
+#define RV_COMPLIANCE_CODE_BEGIN                                              \
+        RVTEST_CODE_BEGIN                                                     \
+
+#define RV_COMPLIANCE_CODE_END                                                \
+        RVTEST_CODE_END                                                       \
+
+#define RV_COMPLIANCE_DATA_BEGIN                                              \
+        .section .test.output;                                                \
+        RVTEST_DATA_BEGIN                                                     \
+
+#define RV_COMPLIANCE_DATA_END                                                \
+        RVTEST_DATA_END                                                       \
+
+#endif
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/Makefile.include
@@ -0,0 +1,74 @@
+# Copyright lowRISC contributors.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+OPENTITAN     = $(ROOTDIR)/riscv-target/$(RISCV_TARGET)/device/rv32imc
+OT_SW         = $(ROOTDIR)/../../device
+OT_ROOT       = $(OT_SW)/../../
+OT_TOOLS     ?= /tools/riscv/bin
+OT_FPGA_UART ?=
+OT_TARGET    ?= fpga
+LDSCRIPT      = $(OPENTITAN)/link.ld
+TRAPHANDLER   = $(OPENTITAN)/handler.S
+DEFINES       = $(CARG) -DPRIV_MISA_S=0 -DPRIV_MISA_U=0 -DTRAPHANDLER="\"$(TRAPHANDLER)\""
+TARGET_SIM   ?= $(OT_ROOT)/build/lowrisc_systems_top_earlgrey_verilator_0.1/sim-verilator/Vtop_earlgrey_verilator
+
+ifeq ($(OT_TARGET),fpga)
+	CARG =
+	MAKEARG =
+	PYTEST_OPT = --fpga_uart $(OT_FPGA_UART) --spiflash $(OT_ROOT)/sw/host/spiflash/spiflash \
+		--test_bin $(work_dir_isa)/$<.bin
+else
+	CARG = -DSIMULATION=1
+	MAKEARG = SIM=1
+	PYTEST_OPT = --verilator_model $(TARGET_SIM) --test_bin $(work_dir_isa)/$<.vmem \
+		--rom_bin $(OT_SW)/boot_rom/rom.vmem
+endif
+
+
+# The run target recipe does the following things:
+# Invoke pytest to run the test
+# Parse the resulting log for the output signatures
+# Convert all signatures to lower case since the reference is in all lower case
+RUN_TARGET=\
+        pytest -s -v $(OT_ROOT)/test/systemtest/functional_$(OT_TARGET)_test.py \
+        $(PYTEST_OPT) \
+        --log $(work_dir_isa)/$<.uart.log; \
+        grep -o 'SIG: [a-zA-Z0-9_]*' $(work_dir_isa)/$<.uart.log | sed 's/SIG: //' \
+        > $(work_dir_isa)/$(*).signature.temp.output; \
+        tr '[:upper:]' '[:lower:]' < $(work_dir_isa)/$(*).signature.temp.output > $(work_dir_isa)/$(*).signature.output;
+
+
+RISCV_PREFIX   ?= ${OT_TOOLS}/riscv32-unknown-elf-
+RISCV_GCC      ?= ${OT_TOOLS}/riscv32-unknown-elf-gcc
+RISCV_OBJDUMP  ?= ${OT_TOOLS}/riscv32-unknown-elf-objdump
+RISCV_OBJCOPY  ?= ${OT_TOOLS}/riscv32-unknown-elf-objcopy
+RISCV_NM       ?= ${OT_TOOLS}/riscv32-unknown-elf-nm
+RISCV_READELF  ?= ${OT_TOOLS}/riscv32-unknown-elf-readelf
+RISCV_GCC_OPTS ?= -static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles -g
+
+
+# The compile target recipe re-uses the boot rom library.
+# This will be changed in the future when the compliance tests directly build
+# their own libraries
+# After the libraries are built, the necessary collateral (vmem for verilator, bin
+# for fpga) are created
+COMPILE_TARGET=\
+        make -C $$(OT_SW) SW_DIR=boot_rom $(MAKEARG) RV_TOOLS=$(OT_TOOLS) clean all; \
+	$$(RISCV_GCC) $(2) $$(RISCV_GCC_OPTS) \
+		-I$(ROOTDIR)/riscv-test-env/ \
+		-I$(ROOTDIR)/riscv-test-env/p/ \
+                -I$(OT_SW)/boot_rom/lib \
+                -I$(OT_SW)/lib \
+		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+		-I$(TARGETDIR)/$(RISCV_TARGET)/ \
+		$(DEFINES) -T$(LDSCRIPT) $$< \
+                $(OPENTITAN)/wrap.c \
+                -L$(OT_SW)/boot_rom/lib \
+                -lot \
+		-o $(work_dir_isa)/$$@; \
+        $$(RISCV_OBJDUMP) -SD $(work_dir_isa)/$$@ > $(work_dir_isa)/[email protected]; \
+        $$(RISCV_READELF) -a $(work_dir_isa)/$$@ > $(work_dir_isa)/[email protected]; \
+        $$(RISCV_NM) $(work_dir_isa)/$$@ > $(work_dir_isa)/[email protected]; \
+        $$(RISCV_OBJCOPY) -O binary $(work_dir_isa)/$$@ $(work_dir_isa)/[email protected]; \
+        srec_cat $(work_dir_isa)/[email protected] -binary -offset 0x0000 -byte-swap 4 -o $(work_dir_isa)/[email protected] -vmem
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/handler.S b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/handler.S
@@ -0,0 +1,22 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+.section .text.trap;
+.align  4;
+
+_trap_start:
+    j _trap_exception
+
+// This could be exception or user interrupt
+// 0xb is the environment call to indicate the end
+_trap_exception:
+    csrr a0, mcause
+    addi a1, zero, 0xb
+    beq a0, a1, _int_exc
+    la a1, begin_signature
+    // write to value pointed by begin_signature and uses a1 as address scratch
+    sw a0, begin_signature, a1
+_int_exc:
+    la a0, write_tohost
+    jr a0
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/isa.yaml b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/isa.yaml
@@ -0,0 +1,49 @@
+## Copyright lowRISC contributors.
+## Licensed under the Apache License, Version 2.0, see LICENSE for details.
+## SPDX-License-Identifier: Apache-2.0
+
+Device: rv32imc
+Vendor: opentitan
+
+ISA: RV32IMC
+misa:
+  implemented: True
+  MXL:
+    range:
+      rangelist: [[1]]
+      mode: Unchanged
+  Extensions:
+    bitmask:
+      mask: 0x0
+      default: 0x1104
+hw_data_misaligned_support: True
+mtvec:
+  MODE:
+    range:
+      rangelist: [[1]]
+  BASE:
+    range:
+      rangelist: [[0x20000020]]
+
+mstatus:
+  MPP:
+    range:
+      rangelist: [[3]]
+
+User_Spec_Version: "2.3"
+Privilege_Spec_Version: "1.11"
+
+mvendorid:
+  implemented: false
+marchid:
+  implemented: false
+mimpid:
+  implemented: false
+mhartid: 0
+
+mcycle:
+  is_hardwired: true
+  implemented: true
+minstret:
+  is_hardwired: true
+  implemented: true
diff --git a/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/link.ld b/sw/vendor/riscv_compliance/riscv-target/opentitan/device/rv32imc/link.ld
@@ -0,0 +1,56 @@
+/* Copyright lowRISC contributors.
+   Licensed under the Apache License, Version 2.0, see LICENSE for details.
+   SPDX-License-Identifier: Apache-2.0
+*/
+
+OUTPUT_ARCH("riscv")
+ENTRY(_start)
+
+/* required to correctly link newlib */
+GROUP(-lc -lgloss -lgcc -lsupc++)
+
+SEARCH_DIR(.)
+__DYNAMIC  =  0;
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x20000000, LENGTH = 0x100000
+    ram (wx)   : ORIGIN = 0x10000000, LENGTH = 0x10000
+}
+
+_stack_start = ORIGIN(ram) + LENGTH(ram);
+
+/* need to move signature data to modifiable memory */
+SECTIONS
+{
+  .text.init ORIGIN(flash) : {
+    *(.text.init)
+  } > flash
+
+  .text.trap : {
+    . = ALIGN(0x100);
+    *(.text.trap)
+  } > flash
+
+  .text : {
+    . = ALIGN(0x100);
+    *(.text)
+  } > flash
+
+  .data : {
+    . = ALIGN(0x100);
+    *(.data.*)
+  } > flash
+
+  .tohost ORIGIN(ram) (NOLOAD) : {
+    *(.tohost)
+    *(.test.output)
+  } > ram
+
+  .bss : {
+    . = ALIGN(0x100);
+    *(.bss)
+  } > ram
+
+  _end = .;
+}