[chip-test] Add volatile_raw_unlock test

This commit adds a new test chip_sw_lc_ctrl_volatile_raw_unlock which exercises the VOLATILE_RAW_UNLOCK functionality in the lc_ctrl. The test enables ROM execution via rv_dm after entering test_unlocked0, and then does a second volatile unlock operation to verify CPU execution. Signed-off-by: Miguel Osorio <[email protected]>
GregAC · May 6, 2023 · 6fb5cba · 6fb5cba
1 parent 752b4b1
commit 6fb5cba
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diff --git a/hw/top_earlgrey/data/chip_testplan.hjson b/hw/top_earlgrey/data/chip_testplan.hjson
@@ -3480,6 +3480,21 @@
               "chip_sw_lc_walkthrough_rma",
               "chip_sw_lc_walkthrough_testunlocks"]
     }
+    {
+      name: chip_sw_lc_ctrl_volatile_raw_unlock
+      desc: '''Configure VOLATILE_RAW_UNLOCK via LC TAP interface and enable CPU execution.
+
+             - Pre-load OTP image with RAW lc_state.
+             - Initiate the LC transition to test_unlocked0 state using the
+               VOLATILE_RAW_UNLOCK mode of operation.
+             - As part of the transition to test_unlocked0, switch the TAP interface to rv_dm.
+             - Enable ROM execution via rv_dm, and perform POR.
+             - Initiate a second transition to test_unlocked0 using VOLATILE_RAW_UNLOCK.
+             - Verify that the CPU is able to execute.
+             '''
+      stage: V2
+      tests: ["chip_sw_lc_ctrl_volatile_raw_unlock"]
+    }
     {
       name: chip_sw_power_max_load
       desc: '''Concurrency test modeling maximum load conditions.

diff --git a/hw/top_earlgrey/dv/chip_sim_cfg.hjson b/hw/top_earlgrey/dv/chip_sim_cfg.hjson
@@ -844,6 +844,14 @@
       run_opts: ["+flash_program_latency=5",
                  "+use_otp_image=OtpTypeLcStRaw", "+dest_dec_state=DecLcStProdEnd"]
     }
+    {
+      name: chip_sw_lc_ctrl_volatile_raw_unlock
+      uvm_test_seq: chip_sw_lc_volatile_raw_unlock_vseq
+      sw_images: ["//sw/device/tests/sim_dv:lc_ctrl_volatile_raw_unlock_test:1"]
+      en_run_modes: ["sw_test_mode_test_rom"]
+      run_opts: ["+use_otp_image=OtpTypeLcStRaw"]
+      run_timeout_mins: 10
+    }
     {
       name: chip_sw_lc_walkthrough_rma
       uvm_test_seq: chip_sw_lc_walkthrough_vseq

diff --git a/hw/top_earlgrey/dv/env/chip_env.core b/hw/top_earlgrey/dv/env/chip_env.core
@@ -93,6 +93,7 @@ filesets:
       - seq_lib/chip_sw_lc_ctrl_transition_vseq.sv: {is_include_file: true}
       - seq_lib/chip_sw_lc_ctrl_scrap_vseq.sv: {is_include_file: true}
       - seq_lib/chip_sw_lc_walkthrough_vseq.sv: {is_include_file: true}
+      - seq_lib/chip_sw_lc_volatile_raw_unlock_vseq.sv: {is_include_file: true}
       - seq_lib/chip_sw_lc_walkthrough_testunlocks_vseq.sv: {is_include_file: true}
       - seq_lib/chip_sw_lc_ctrl_program_error_vseq.sv: {is_include_file: true}
       - seq_lib/chip_sw_otp_ctrl_vendor_test_csr_access_vseq.sv: {is_include_file: true}

diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_base_vseq.sv
@@ -720,6 +720,70 @@ class chip_sw_base_vseq extends chip_base_vseq;
     cfg.m_jtag_riscv_agent_cfg.allow_errors = 0;
   endtask
 
+  // Use JTAG interface to transit LC_CTRL from RAW to TEST_UNLOCKED* states
+  // using the VOLATILE_RAW_UNLOCK mode of operation.
+  virtual task jtag_lc_state_volatile_raw_unlock(chip_jtag_tap_e target_strap);
+    bit [TL_DW-1:0] current_lc_state;
+    bit [TL_DW-1:0] transition_ctrl;
+    int max_attempt = 5_000;
+    dec_lc_state_e dest_state = DecLcStTestUnlocked0;
+
+    wait_lc_ready();
+    jtag_riscv_agent_pkg::jtag_read_csr(ral.lc_ctrl.lc_state.get_offset(),
+                                        p_sequencer.jtag_sequencer_h,
+                                        current_lc_state);
+    `DV_CHECK_EQ(DecLcStRaw, current_lc_state)
+
+    `uvm_info(`gfn, $sformatf("Start LC transition request to %0s state", dest_state.name),
+                              UVM_LOW)
+    jtag_riscv_agent_pkg::jtag_write_csr(ral.lc_ctrl.claim_transition_if.get_offset(),
+                                         p_sequencer.jtag_sequencer_h,
+                                         prim_mubi_pkg::MuBi8True);
+
+    `uvm_info(`gfn, "Switching to VOLATILE_RAW_UNLOCK via JTAG...", UVM_LOW)
+    jtag_riscv_agent_pkg::jtag_write_csr(
+      ral.lc_ctrl.transition_ctrl.get_offset(),
+      p_sequencer.jtag_sequencer_h,
+      2);
+
+    jtag_riscv_agent_pkg::jtag_read_csr(
+      ral.lc_ctrl.transition_ctrl.get_offset(),
+      p_sequencer.jtag_sequencer_h,
+      transition_ctrl);
+    `DV_CHECK_FATAL(transition_ctrl & (1 << 1), {"VOLATILE_RAW_UNLOCK is not supported by this ",
+                    "top level. Check the SecVolatileRawUnlockEn parameter configuration."})
+
+    begin
+      bit [TL_DW-1:0] token_csr_vals[4] = {<< 32 {{>> 8 {RndCnstRawUnlockTokenHashed}}}};
+      foreach (token_csr_vals[index]) begin
+        jtag_riscv_agent_pkg::jtag_write_csr(ral.lc_ctrl.transition_token[index].get_offset(),
+                                             p_sequencer.jtag_sequencer_h,
+                                             token_csr_vals[index]);
+      end
+    end
+
+    // Switch strap configuration before requesting volatile raw unlock. This is to
+    // switch to rv_dm in test_unlocked0.
+    cfg.chip_vif.tap_straps_if.drive(target_strap);
+
+    `uvm_info(`gfn, "Sent LC transition request", UVM_LOW)
+    jtag_riscv_agent_pkg::jtag_write_csr(ral.lc_ctrl.transition_target.get_offset(),
+                                         p_sequencer.jtag_sequencer_h,
+                                         {DecLcStateNumRep{DecLcStTestUnlocked0}});
+    jtag_riscv_agent_pkg::jtag_write_csr(ral.lc_ctrl.transition_cmd.get_offset(),
+                                         p_sequencer.jtag_sequencer_h,
+                                         1);
+
+    if (target_strap == JtagTapLc) begin
+      wait_lc_transition_successful(.max_attempt(max_attempt));
+      jtag_riscv_agent_pkg::jtag_write_csr(ral.lc_ctrl.claim_transition_if.get_offset(),
+                                         p_sequencer.jtag_sequencer_h,
+                                         prim_mubi_pkg::MuBi8False);
+    end else begin
+      cfg.clk_rst_vif.wait_clks($urandom_range(10000, 20000));
+    end
+  endtask
+
   // Use JTAG interface to transit LC_CTRL from one state to the valid next state.
   // Currently support the following transitions:
   // 1). RAW state -> test unlock state N

diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_sw_lc_volatile_raw_unlock_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_sw_lc_volatile_raw_unlock_vseq.sv
@@ -0,0 +1,60 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class chip_sw_lc_volatile_raw_unlock_vseq extends chip_sw_base_vseq;
+  `uvm_object_utils(chip_sw_lc_volatile_raw_unlock_vseq)
+
+  `uvm_object_new
+
+  virtual task pre_start();
+    cfg.chip_vif.tap_straps_if.drive(JtagTapLc);
+    super.pre_start();
+  endtask
+
+  // reset jtag interface
+  virtual task reset_jtag_tap();
+    cfg.m_jtag_riscv_agent_cfg.in_reset = 1;
+    #1000ns;
+    cfg.m_jtag_riscv_agent_cfg.in_reset = 0;
+  endtask
+
+  virtual task body();
+    bit [TokenWidthBit-1:0] otp_exit_token_bits, otp_unlock_token_bits, otp_rma_token_bits;
+    bit [7:0] selected_dest_state[];
+
+    jtag_riscv_dm_activation_seq jtag_dm_activation_seq =
+        jtag_riscv_dm_activation_seq::type_id::create("jtag_dm_activation_seq");
+
+    super.body();
+
+    wait_lc_ready(1);
+
+    // VOLATILE_RAW_UNLOCK does not require a reset after completion.
+    // Applying a reset will move the device back to RAW state in this case.
+    jtag_lc_state_volatile_raw_unlock(JtagTapRvDm);
+    reset_jtag_tap();
+
+    // In RAW state the ROM should halt as RomExecEn is not set yet.
+    `DV_WAIT(cfg.sw_test_status_vif.sw_test_status == SwTestStatusInBootRomHalt)
+
+    // Use the frontend interface to configure the RomExecEn OTP value. A
+    // reset is required to have otp_ctrl sample the new OTP value.
+    `uvm_info(`gfn, "Configuring RomExecEng", UVM_LOW)
+    jtag_dm_activation_seq.start(p_sequencer.jtag_sequencer_h);
+    `uvm_info(`gfn, $sformatf("rv_dm_activated: %0d", cfg.m_jtag_riscv_agent_cfg.rv_dm_activated),
+            UVM_LOW)
+    cfg.m_jtag_riscv_agent_cfg.is_rv_dm = 1;
+    jtag_otp_program32(otp_ctrl_reg_pkg::CreatorSwCfgRomExecEnOffset, 1);
+
+    cfg.chip_vif.tap_straps_if.drive(JtagTapLc);
+    cfg.m_jtag_riscv_agent_cfg.is_rv_dm = 0;
+    apply_reset();
+
+    // Second VOLATILE_RAW_UNLOCK does not change the TAP interface to rv_dm
+    // so that we can check the completion status through that interface.
+    // After this, the rest of the test should proceed.
+    jtag_lc_state_volatile_raw_unlock(JtagTapLc);
+
+  endtask
+endclass
diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_vseq_list.sv
@@ -39,6 +39,7 @@
 `include "chip_sw_flash_rma_unlocked_vseq.sv"
 `include "chip_sw_lc_ctrl_transition_vseq.sv"
 `include "chip_sw_lc_ctrl_scrap_vseq.sv"
+`include "chip_sw_lc_volatile_raw_unlock_vseq.sv"
 `include "chip_sw_lc_walkthrough_vseq.sv"
 `include "chip_sw_lc_walkthrough_testunlocks_vseq.sv"
 `include "chip_sw_otp_ctrl_vendor_test_csr_access_vseq.sv"

diff --git a/sw/device/tests/sim_dv/BUILD b/sw/device/tests/sim_dv/BUILD
@@ -332,6 +332,23 @@ opentitan_functest(
     ],
 )
 
+opentitan_functest(
+    name = "lc_ctrl_volatile_raw_unlock_test",
+    srcs = ["lc_ctrl_volatile_raw_unlock_test.c"],
+    targets = ["dv"],
+    deps = [
+        "//hw/top_earlgrey/sw/autogen:top_earlgrey",
+        "//sw/device/lib/base:bitfield",
+        "//sw/device/lib/base:memory",
+        "//sw/device/lib/base:mmio",
+        "//sw/device/lib/dif:lc_ctrl",
+        "//sw/device/lib/runtime:log",
+        "//sw/device/lib/testing:lc_ctrl_testutils",
+        "//sw/device/lib/testing/test_framework:check",
+        "//sw/device/lib/testing/test_framework:ottf_main",
+    ],
+)
+
 opentitan_functest(
     name = "lc_walkthrough_test",
     srcs = ["lc_walkthrough_test.c"],

diff --git a/sw/device/tests/sim_dv/lc_ctrl_volatile_raw_unlock_test.c b/sw/device/tests/sim_dv/lc_ctrl_volatile_raw_unlock_test.c
@@ -0,0 +1,31 @@
+// Copyright lowRISC contributors.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+#include <assert.h>
+#include <stdbool.h>
+
+#include "sw/device/lib/base/bitfield.h"
+#include "sw/device/lib/base/memory.h"
+#include "sw/device/lib/base/mmio.h"
+#include "sw/device/lib/dif/dif_lc_ctrl.h"
+#include "sw/device/lib/runtime/log.h"
+#include "sw/device/lib/testing/lc_ctrl_testutils.h"
+#include "sw/device/lib/testing/test_framework/check.h"
+#include "sw/device/lib/testing/test_framework/ottf_main.h"
+
+#include "hw/top_earlgrey/sw/autogen/top_earlgrey.h"
+
+static dif_lc_ctrl_t lc_ctrl;
+
+OTTF_DEFINE_TEST_CONFIG();
+
+bool test_main(void) {
+  CHECK_DIF_OK(dif_lc_ctrl_init(
+      mmio_region_from_addr(TOP_EARLGREY_LC_CTRL_BASE_ADDR), &lc_ctrl));
+
+  dif_lc_ctrl_state_t state;
+  CHECK_DIF_OK(dif_lc_ctrl_get_state(&lc_ctrl, &state));
+  CHECK(state == kDifLcCtrlStateTestUnlocked0);
+  return true;
+}