test_iostream: refactor sampling to make it use .sample()

This better relays the intent that we want to sample the
"old" value of the inputs in case they change at the same time
as clk_out, and may work better if input_generator_tb changes
in the future.

software/tests/gateware/test_iostream.py

@@ -119,8 +119,7 @@ async def save_expected_sample_values_tb(ctx):
             """
             while True:
                 # in the case of SDR tests there are no glitches on the clock_out simulation, so we case safely use ctx.changed:
-                await ctx.changed(ports.clk_out.o)
-                value = ctx.get(ports.data_in.i)
+                _, value = await ctx.changed(ports.clk_out.o).sample(ports.data_in.i)
                 expected_sample.append(value)
 
         async def i_stream_consumer_tb(ctx):
@@ -279,23 +278,24 @@ async def save_expected_sample_values_tb(ctx):
             later, when the sample actually arrives back on i_stream.
             The way we look for the rising edge is a bit hairy, because the current implementation of
             DDRBufferCanBeSimulated can generate glitches, so we wait DELAY_TO_AVOID_GLITCHES after
-            the clock edge, to make sure any glitches are resolved.
-            Because this is a DDR test, we also wait half a clock to save the other edge as well.
+            the clock edge, to make sure any glitches are resolved, and if the clock signal doesn't have
+            the expected value, then we throw away the sampled data, and wait for a clock edge again.
+            Because this is a ddr test, we check both edge of clk_out one after the other.
             """
             while True:
                 DELAY_TO_AVOID_GLITCHES = CLK_PERIOD/10
 
-                await ctx.posedge(ports.clk_out.o[0])
-                await ctx.delay(DELAY_TO_AVOID_GLITCHES)
-                while ctx.get(ports.clk_out.o[0]) == 0:
-                    await ctx.posedge(ports.clk_out.o[0])
+                while True:
+                    _, value_phase_0 = await ctx.posedge(ports.clk_out.o).sample(ports.data_in.i)
                     await ctx.delay(DELAY_TO_AVOID_GLITCHES)
+                    if ctx.get(ports.clk_out.o) == 1:
+                        break
 
-                value_phase_0 = ctx.get(ports.data_in.i)
-
-                await ctx.delay(CLK_PERIOD / 2)
-
-                value_phase_1 = ctx.get(ports.data_in.i)
+                while True:
+                    _, value_phase_1 = await ctx.negedge(ports.clk_out.o).sample(ports.data_in.i)
+                    await ctx.delay(DELAY_TO_AVOID_GLITCHES)
+                    if ctx.get(ports.clk_out.o) == 0:
+                        break
 
                 expected_sample.append((value_phase_0, value_phase_1))