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Fayz2110/README.md

Hi 👋, I'm Fayz

A passionate Hardware design Engineer from Pakistan, with expertise in Verilog, SystemC and system Verilog

Coding

Fayz2110

Fayz2110

Connect with me:

fayz tauseef

Languages and Tools:

c cplusplus git linux matlab mysql python

Top Languages

 Fayz2110's GitHub Stats

Fayz2110's GitHub Streak

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  1. Executing-Assembly-on-SPIKE-RISC-V-Simulator Executing-Assembly-on-SPIKE-RISC-V-Simulator Public

    Assembly

  2. merledu/rv-thunder merledu/rv-thunder Public

    RISC-V 32-bit CPU written in amaranth (python-lib)

    Verilog 9 5