Merge branch 'main' of https://github.com/FPGAwars/iceWires

FPGAwars · Nov 4, 2023 · eb9a0f2 · eb9a0f2
2 parents eaaff76 + 8398634
commit eb9a0f2
Showing 1 changed file with 9 additions and 15 deletions.
diff --git a/locale/translation.js b/locale/translation.js
@@ -2081,36 +2081,29 @@ gettext('14-bits');
 gettext('15-bits');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT32-8bit-verilog:  Extend a 8-bit unsigned integer to 32-bits. Verilog implementation ');
-gettext('## Uint16-8bit Manual testing');
+gettext('## 08-Uint16 Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT32-9bit-verilog:  Extend a 9-bit unsigned integer to 32-bits. Verilog implementation ');
+gettext('## 09-Uint16 Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT32-10bit-verilog:  Extend a 10-bit unsigned integer to 32-bits. Verilog implementation ');
-gettext('## Uint16-10bit Manual testing');
+gettext('## 10-Uint16 Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT32-11bit-verilog:  Extend a 11-bit unsigned integer to 32-bits. Verilog implementation ');
-gettext('## Uint16-11bit Manual testing');
+gettext('## 11-Uint16 Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT32-12bit-verilog:  Extend a 12-bit unsigned integer to 32-bits. Verilog implementation ');
-gettext('## Uint16-12bit Manual testing');
+gettext('## 12-Uint16 Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT32-13bit-verilog:  Extend a 13-bit unsigned integer to 32-bits. Verilog implementation ');
-gettext('## Uint16-13bit Manual testing');
+gettext('## 13-Uint16 Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT32-14bit-verilog:  Extend a 14-bit unsigned integer to 32-bits. Verilog implementation ');
-gettext('## Uint16-14bit Manual testing');
+gettext('## 14-Uint16 Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
-gettext('UINT32-15bit-verilog:  Extend a 15-bit unsigned integer to 32-bits. Verilog implementation ');
 gettext('Copy-15: Copy the input wire twice and generate a 15 bits Bus output (Verilog implementation)');
-gettext('## Uint32-15bit Manual testing');
+gettext('## 15-Uint32 Manual testing');
 gettext('02-bits');
 gettext('08-bits');
 gettext('16-bits');
@@ -2135,6 +2128,7 @@ gettext('not-x32: 32-bits not gate');
 gettext('## Uint32-2bit Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');
+gettext('UINT32-8bit-verilog:  Extend a 8-bit unsigned integer to 32-bits. Verilog implementation ');
 gettext('## Uint32-8bit Manual testing');
 gettext('Alhambra-II');
 gettext('01-Manual-testing');