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Merge branch 'main' of https://github.com/FPGAwars/iceWires
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Obijuan committed Nov 4, 2023
2 parents c35aec8 + 3f8a6fc commit e71f175
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13 changes: 7 additions & 6 deletions README.md
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Expand Up @@ -1263,12 +1263,13 @@ For installing and using this colection in Icestudio follow these steps:
* **Alhambra-II**
* 01-Manual-testing
* **Uint32**
* **02-bits**
* **Alhambra-II**
* 01-Manual-testing
* **08-bits**
* **Alhambra-II**
* 01-Manual-testing
* **02-08-bits**
* **02-bits**
* **Alhambra-II**
* 01-Manual-testing
* **08-bits**
* **Alhambra-II**
* 01-Manual-testing
* **16-bits**
* **Alhambra-II**
* 01-Manual-testing
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5 changes: 3 additions & 2 deletions locale/translation.js
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Expand Up @@ -2104,8 +2104,7 @@ gettext('Alhambra-II');
gettext('01-Manual-testing');
gettext('Copy-15: Copy the input wire twice and generate a 15 bits Bus output (Verilog implementation)');
gettext('## 15-Uint32 Manual testing');
gettext('02-bits');
gettext('08-bits');
gettext('02-08-bits');
gettext('16-bits');
gettext('17-bits');
gettext('18-bits');
Expand All @@ -2122,6 +2121,8 @@ gettext('28-bits');
gettext('29-bits');
gettext('30-bits');
gettext('31-bits');
gettext('02-bits');
gettext('08-bits');
gettext('Alhambra-II');
gettext('01-Manual-testing');
gettext('not-x32: 32-bits not gate');
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