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ulx3s-12f: ledon example with testbench for simulation
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Obijuan committed Apr 28, 2022
1 parent a87560d commit b7ad21e
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3 changes: 3 additions & 0 deletions ulx3s-12f/ledon/apio.ini
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[env]
board = ulx3s-12f

1 change: 1 addition & 0 deletions ulx3s-12f/ledon/info
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Hello world for the ulx3s board: Turn on the LED0
15 changes: 15 additions & 0 deletions ulx3s-12f/ledon/ledon.v
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//------------------------------------------------------------------
//-- Turn on one LED
//------------------------------------------------------------------
module led_on(
output [7:0] led //-- LEDs
);

//-- LED0 on
assign led[0] = 1'b1;

//-- The other LEDs are off
assign led[7:1] = 6'b0;

endmodule

29 changes: 29 additions & 0 deletions ulx3s-12f/ledon/ledon_tb.gtkw
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[*]
[*] GTKWave Analyzer v3.3.103 (w)1999-2019 BSI
[*] Thu Apr 28 07:18:35 2022
[*]
[dumpfile] "/home/obijuan/Develop/FPGAwars/apio-examples/ulx3s-12f/ledon/ledon_tb.vcd"
[dumpfile_mtime] "Thu Apr 28 07:14:34 2022"
[dumpfile_size] 462
[savefile] "/home/obijuan/Develop/FPGAwars/apio-examples/ulx3s-12f/ledon/ledon_tb.gtkw"
[timestart] 0
[size] 1920 1043
[pos] -39 -39
*-7.038382 49 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] ledon_tb.
[sst_width] 233
[signals_width] 111
[sst_expanded] 1
[sst_vpaned_height] 298
@28
ledon_tb.led7
ledon_tb.led6
ledon_tb.led5
ledon_tb.led4
ledon_tb.led3
ledon_tb.led2
ledon_tb.led1
@29
ledon_tb.led0
[pattern_trace] 1
[pattern_trace] 0
36 changes: 36 additions & 0 deletions ulx3s-12f/ledon/ledon_tb.v
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//-------------------------------------------------------------------
//-- ledon_tb.v
//-- Testbench
//-------------------------------------------------------------------
//-- Juan Gonzalez (Obijuan)
//-- GPL license
//-------------------------------------------------------------------
`default_nettype none
`define DUMPSTR(x) `"x.vcd`"
`timescale 100 ns / 10 ns

module ledon_tb();

//-- Simulation time: 1us (10 * 100ns)
parameter DURATION = 10;

//-- Leds port
wire led0, led1, led2, led3, led4, led5, led6, led7;

//-- Instantiate the unit to test
led_on UUT (
.led({led7, led6, led5, led4, led3, led2, led1, led0})
);


initial begin

//-- File were to store the simulation results
$dumpfile(`DUMPSTR(`VCD_OUTPUT));
$dumpvars(0, ledon_tb);

#(DURATION) $display("End of simulation");
$finish;
end

endmodule
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