EDU-CIAA-FPGA: Template added

EDU-CIAA-FPGA/Template/apio.ini

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+[env]
+board = edu-ciaa-fpga
+

EDU-CIAA-FPGA/Template/info

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+Project template for the EDU-CIAA-FPGA board

EDU-CIAA-FPGA/Template/pinout.pcf

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+# -----------------------------------------------------------------------------
+#- EDU-CIAA-FPGA constraint file (.pcf)
+#- Sep - 2020
+#- GPL license
+#- Repo: https://gitlab.com/educiaafpga
+#- Pinout: https://github.com/ciaa/Hardware/blob/master/PCB/EDU-FPGA/Pinout/Pinout%20EDU%20FPGA.pdf
+# -----------------------------------------------------------------------------
+
+#------ User LEDs
+set_io --warn-no-port LED3 4  #-- output 
+set_io --warn-no-port LED2 3  #-- output
+set_io --warn-no-port LED1 2  #-- output 
+set_io --warn-no-port LED0 1  #-- output
+
+# ------------ User push buttons ----------------------------------------------
+set_io --warn-no-port BTN1 31  # input
+set_io --warn-no-port BTN2 32  # input
+set_io --warn-no-port BTN3 33  # input
+set_io --warn-no-port BTN4 34  # input
+
+# ------------- Digital I/O ---------------------------------
+
+# ---- B1 Header
+# -- Left column
+set_io --warn-no-port B1_21 107
+set_io --warn-no-port B1_19 105
+set_io --warn-no-port B1_17 99
+set_io --warn-no-port B1_15 97
+set_io --warn-no-port B1_13 95
+set_io --warn-no-port B1_11 84
+set_io --warn-no-port B1_9  89
+set_io --warn-no-port B1_7  80
+
+# -- Right column
+set_io --warn-no-port B1_20 106
+set_io --warn-no-port B1_18 104
+set_io --warn-no-port B1_16 98
+set_io --warn-no-port B1_14 96
+set_io --warn-no-port B1_12 85
+set_io --warn-no-port B1_10 83
+set_io --warn-no-port B1_8  81
+set_io --warn-no-port B1_6  79
+
+# ---- B0 Header
+# -- Left column
+set_io --warn-no-port B0_1 122
+set_io --warn-no-port B0_3 125
+set_io --warn-no-port B0_5 129
+set_io --warn-no-port B0_7 134
+set_io --warn-no-port B0_9 136
+set_io --warn-no-port B0_11 138
+set_io --warn-no-port B0_13 141
+set_io --warn-no-port B0_14 142
+
+# -- Right column
+set_io --warn-no-port B0_2 124
+set_io --warn-no-port B0_4 128
+set_io --warn-no-port B0_6 130
+set_io --warn-no-port B0_8 135
+set_io --warn-no-port B0_10 137
+set_io --warn-no-port B0_12 139
+set_io --warn-no-port B0_15 143
+set_io --warn-no-port B0_16 144
+
+# ---- B3 Header
+# -- Left connector
+set_io --warn-no-port B3_5 11
+set_io --warn-no-port B3_6 12
+set_io --warn-no-port B3_7 15
+set_io --warn-no-port B3_8 16
+set_io --warn-no-port B3_1 7
+set_io --warn-no-port B3_2 8
+set_io --warn-no-port B3_3 9
+set_io --warn-no-port B3_4 10
+
+# -- Right connector
+set_io --warn-no-port B3_13 21
+set_io --warn-no-port B3_14 22
+set_io --warn-no-port B3_15 23
+set_io --warn-no-port B3_16 24
+set_io --warn-no-port B3_9  17
+set_io --warn-no-port B3_10 18
+set_io --warn-no-port B3_11 19
+set_io --warn-no-port B3_12 20
+
+# -------------------------- SYSTEM CLOCK -------------------------------------
+set_io --warn-no-port CLK 94  # input
+
+# ------------ Reset ---------------
+set_io --warn-no-port RST 37  # input
+
+# -------------------------- FTDI ---------------------------------------------
+# --- FTDI 1: (Serial port)
+set_io --warn-no-port RX  55  # input
+set_io --warn-no-port TX  56  # output
+set_io --warn-no-port RTS 60  # input
+set_io --warn-no-port CTS 61  # output
+set_io --warn-no-port DTR 62  # input
+set_io --warn-no-port DSR 63  # output
+set_io --warn-no-port DCD 65  # output
+

EDU-CIAA-FPGA/Template/test.v

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+//------------------------------------------------------------------
+//-- Top-level Verilog example
+//------------------------------------------------------------------
+
+module Test (
+  input CLK,    // 12MHz clock
+  output LED0   // D6
+);
+
+  reg [23:0] counter = 0;
+
+  always @(posedge CLK) 
+    counter <= counter + 1;
+
+  assign LED0 = counter[23];
+
+endmodule