Building blocks for SpinalHDL designs

This repository contains some useful constructs I use to build hardware in SpinalHDL. Significant pieces include:

• Register allocator with blocks management and C header generation
• Profiler for taking timestamps and passing them around in the design
• verilog-axi blackboxes for the Verilog AXI IP library
• ECI definitions for various definitions for the ECI toolkit and using the Directory Controller Slice with Enzian.