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v4.1 After Second Design Review
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@AngeloJacobo AngeloJacobo released this 16 Jun 13:54
· 229 commits to main since this release
v4.1
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Learn about vigilant mode.

Fix

  • Moved assembly testfiles (extra/) and all test scripts (test.sh, sections.py, wave.do) to a single folder /test. This makes the repository more orderly
  • Moved the rv32i_soc_TB.v from rtl/ to test/ to separate testbench from the synthesizable verilog files
  • Script will now first check if riscv-tests/ exists. If not, clone the repository from here. This ensures latest updates on riscv-tests will be integrated on the regression tests
  • Added i_ and o_ prefixes for all input and output pins for an easier distinction of pin connections
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