v4.0 RISC-V Compliant

rv32ui (RV32 User-Mode Integer-Only) and rv32mi (RV32 Machine-Mode Integer-Only) testfiles from RISC-V International are now part of the regression tests. All tests passed.

Fix

• Instruction address misaligned exception is now thrown at the taken branch or jump instruction (previous implementation throws an exception after jumping or branching to the misaligned instruction address). Decoding logic for is_inst_addr_misaligned is now moved from rv32i_decoder to rv32i_csr since the ALU [EXECUTE STAGE] must first compute the address to know if address is misaligned.
• Instruction memory and Data memory are now merged into one regfile. This is to pass fence_i.S tesfile. The interface for instruction and data are still separate.

New

• riscv-tests/ folder = contains the RISC-V International RV32I tests
• riscv-test-env/ folder = contains the test environment necessary for running the RISCV International RV32I tests
• extra/ folder = this is the previous folder named testbank which contains my own assembly testfiles