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v1.1 After Design Review
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@AngeloJacobo AngeloJacobo released this 18 Mar 10:43
· 305 commits to main since this release
v1.1
1d1c468

Fix

  • Replaced all tabs with spaces for better alignment
  • Registered all outputs of modules to reduce long timing paths
  • Removed cross-referencing of parameters by using single-bit decoding
  • Removed basereg initialization to zero (spec does not require basereg, except x0, to be initialized to zero)
  • Wrapped up FSM to its own module: rv32i_fsm
  • Solved warnings from Modelsim simulation

New

  • scripts for automatic simulation with Modelsim and Vivado
Assets 2
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