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v1.0 First Working Implementation
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@AngeloJacobo AngeloJacobo released this 17 Mar 02:36
· 344 commits to main since this release
v1.0
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Learn about vigilant mode.

My first working implementation of RV32 Integer core.This is FSM based (no pipelining) and no CSR yet. A simple testbench (executes a hexfile for instruction) is used to verify the core.

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