display returned instructions and clock cycle count at the end

AngeloJacobo · Jun 23, 2022 · 7092cc4 · 7092cc4
1 parent aac05ad
commit 7092cc4
Showing 1 changed file with 2 additions and 2 deletions.
diff --git a/test/rv32i_soc_TB.v b/test/rv32i_soc_TB.v
@@ -145,9 +145,9 @@ module rv32i_soc_TB #(parameter MEMORY);
 
         if(uut.m0.m0.base_regfile[17] == 32'h5d) begin //Exit test using RISC-V International's riscv-tests pass/fail criteria
             if(uut.m0.m0.base_regfile[10] == 0)
-                $display("\nPASS: exit code = 0x%h",uut.m0.m0.base_regfile[10]>>1);
+                $display("\nPASS: exit code = 0x%h \n[%0d instructions in %0d clk cycles]\n",uut.m0.m0.base_regfile[10]>>1,uut.m0.m6.minstret,uut.m0.m6.mcycle);
             else begin
-                $display("\nFAIL: exit code = 0x%h",uut.m0.m0.base_regfile[10]>>1);
+                $display("\nFAIL: exit code = 0x%h \n[%0d instructions in %0d clk cycles]\n",uut.m0.m0.base_regfile[10]>>1,uut.m0.m6.minstret,uut.m0.m6.mcycle);
             end
         end
         else $display("\nUNKNOWN: basereg[17] = 0x%h (must be 0x0000005d)",uut.m0.m0.base_regfile[17]);