AY3891x v2.0.0

What's Changed

• Decrease tDW by @berarma in #3
• Optimized bus control signal timing for all state changes (inspired by above pull request) (merged in #4)
• Clarified README and constructor comments to note that BDIR, BC2, BC1 are required signals for this library to work correctly

Note

• The library API did not change
• The bus control signal timing changed. In particular, the duration of the READ and WRITE signals to the chip will have decreased. On a 16 MHz ATmega 328, the access times changed from about 15 us to 4.5 us
  • This is particularly important for the WRITE case, as most datasheets list a maximum WRITE time (tDW) of 10 us
• Interrupts are disabled for about 4.5 us during a WRITE operation
  • This ensures a consistent WRITE timing
  • Previous versions of this library did not disable interrupts
• These changes should typically have no negative affect on any existing code, but code that is particularly dependent on timing may behave differently with this version

New Contributors

• @berarma made their first contribution in #3

Full Changelog: v1.1.3...v2.0.0