am64xr5: change DDR MPU settings to Normal, Cacheable

The default MPU memory map of the am64xr5 runtime marks the DDR memory as
non-sharable device memory. However device memory is designed for
memory-mapped peripherals, so doesn't allow execution even if we explicitly
mark it as execute enabled.

To be more customer friendly, change this memory region to be cacheable
normal memory (which really it is).

Issue: eng/toolchain/bb-runtimes#53
(cherry picked from commit 02e7a90)

src/s-boapar__am64xr5.ads

@@ -137,6 +137,6 @@ package System.Board_Parameters is
             Access_Control  =>
               (XN                 => MD.Execute_All,
                AP                 => MD.Privileged_RW_User_RW,
-               TEX_S_C_B          => MD.Non_Shareable_Device))
+               TEX_S_C_B          => MD.Outer_Inner_WB_WA_NS))
      );
 end System.Board_Parameters;