Merge remote-tracking branch 'origin/master' into release

README.md

@@ -17,7 +17,7 @@ A few tests are executed by running the SBSA ACS Linux application which in turn
 
 
 ## Release details
- - Code Quality: REL v1.2
+ - Code Quality: REL v1.3
  - The tests are written for version 3.0 of the SBSA specification.
  - The compliance suite is not a substitute for design verification.
  - To review the SBSA ACS logs, ARM licensees can contact ARM directly through their partner managers.

docs/testcase-checklist.md

@@ -60,8 +60,8 @@
 | 56             | PCIe                             | L0+   | In a system with a SMMU for PCI express there are no transformations to addresses being sent by PCI express devices before they are presented as an input address to the SMMU.                                                                                                                                 | 8.3             | yes                | Linux driver               |
 | 56             | PCIe                             | L3+   | the addresses sent by PCI express devices must be presented to the memory system or SMMU unmodified                                                                                                                                                                                                            | 4.4.8           | yes                | Linux driver               |
 | 57             | PCIe                             | L1+   | Support for Message Signaled Interrupts (MSI/MSI-X) is required for PCI Express devices. MSI and MSI-X are edge-triggered interrupts that are delivered as a memory write transaction                                                                                                                          | 8.4             | yes                | Linux driver               |
-| 58             | PCIe                             | L1+   | each unique MSI(-X) shall trigger an interrupt with a unique ID and the MSI(-X) shall target GIC registers requiring no hardware specific software to service the interrupt                                                                                                                                    | 8.4             | yes                | Linux driver               |
-| 58             | PCIe                             | L1+   | Add GICv2/v3 support details                                                                                                                                                                                                                                                                                   | 8.4.1/2         | yes                | Linux driver               |
+|                | PCIe                             | L1+   | each unique MSI(-X) shall trigger an interrupt with a unique ID and the MSI(-X) shall target GIC registers requiring no hardware specific software to service the interrupt                                                                                                                                    | 8.4             | No                 | Linux driver               |
+|                | PCIe                             | L1+   | Add GICv2/v3 support details                                                                                                                                                                                                                                                                                   | 8.4.1/2         | No                 | Linux driver               |
 | 59             | GICv3                            | L2+   | All MSIs and MSI-x are mapped to LPI                                                                                                                                                                                                                                                                           | 4.3.2           | yes                | Linux driver               |
 | 60             | PCIe                             | L3+   | If the system supports PCIe PASID, then at least 16 bits of PASID must be supported                                                                                                                                                                                                                            | 8.11            | yes                | Linux driver               |
 | 61             | PCIe                             | L0+   | The PCI Express root complex is in the same Inner Shareable domain as the PEs                                                                                                                                                                                                                                  | 8.7             | yes                | Linux driver               |

linux_app/sbsa-acs-app/include/sbsa_app.h

@@ -20,7 +20,7 @@
 
 
 #define SBSA_APP_VERSION_MAJOR  1
-#define SBSA_APP_VERSION_MINOR  2
+#define SBSA_APP_VERSION_MINOR  3
 
 #include "sbsa_drv_intf.h"
 

platform/pal_uefi/include/pal_iovirt.h

@@ -89,6 +89,12 @@ typedef struct {
         UINT32 gerr_gsiv;
         UINT32 sync_gsiv;
 }IORT_SMMU_V3;
+
+typedef struct {
+        UINT64 base_address;
+        UINT32 overflow_interrupt_gsiv;
+        UINT32 node_reference;
+}IORT_PMCG;
 #pragma pack()
 
 #endif

platform/pal_uefi/include/pal_uefi.h

@@ -26,6 +26,8 @@ extern UINT32 g_print_level;
 #define AVS_PRINT_DEBUG 2      /* For Debug statements. contains register dumps etc */
 #define AVS_PRINT_INFO  1      /* Print all statements. Do not use unless really needed */
 
+#define PCIE_READ_ERR -1
+
 typedef struct {
   UINT64   Arg0;
   UINT64   Arg1;
@@ -182,23 +184,30 @@ typedef struct {
 }SMMU_INFO_BLOCK;
 
 typedef struct {
-	UINT32 segment;
-	UINT32 ats_attr;
-	UINT32 cca;			//Cache Coherency Attribute
+  UINT32 segment;
+  UINT32 ats_attr;
+  UINT32 cca;             //Cache Coherency Attribute
 }IOVIRT_RC_INFO_BLOCK;
 
+typedef struct {
+  UINT64 base;
+  UINT32 overflow_gsiv;
+  UINT32 node_ref;
+} IOVIRT_PMCG_INFO_BLOCK;
+
 typedef enum {
   IOVIRT_NODE_ITS_GROUP = 0x00,
   IOVIRT_NODE_NAMED_COMPONENT = 0x01,
   IOVIRT_NODE_PCI_ROOT_COMPLEX = 0x02,
   IOVIRT_NODE_SMMU = 0x03,
-  IOVIRT_NODE_SMMU_V3 = 0x04
+  IOVIRT_NODE_SMMU_V3 = 0x04,
+  IOVIRT_NODE_PMCG = 0x05
 }IOVIRT_NODE_TYPE;
 
 typedef enum {
-        IOVIRT_FLAG_DEVID_OVERLAP_SHIFT,
-        IOVIRT_FLAG_STRID_OVERLAP_SHIFT,
-        IOVIRT_FLAG_SMMU_CTX_INT_SHIFT,
+  IOVIRT_FLAG_DEVID_OVERLAP_SHIFT,
+  IOVIRT_FLAG_STRID_OVERLAP_SHIFT,
+  IOVIRT_FLAG_SMMU_CTX_INT_SHIFT,
 }IOVIRT_FLAG_SHIFT;
 
 typedef struct {
@@ -216,6 +225,7 @@ typedef union {
 typedef union {
   CHAR8 name[16];
   IOVIRT_RC_INFO_BLOCK rc;
+  IOVIRT_PMCG_INFO_BLOCK pmcg;
   UINT32 its_count;
   SMMU_INFO_BLOCK smmu;
 }NODE_DATA;
@@ -234,6 +244,7 @@ typedef struct {
   UINT32 num_pci_rcs;
   UINT32 num_named_components;
   UINT32 num_its_groups;
+  UINT32 num_pmcgs;
   IOVIRT_BLOCK blocks[];
 }IOVIRT_INFO_TABLE;
 

platform/pal_uefi/src/pal_iovirt.c

@@ -65,7 +65,12 @@ dump_block(IOVIRT_BLOCK *block) {
       break;
       case IOVIRT_NODE_SMMU:
       case IOVIRT_NODE_SMMU_V3:
-      sbsa_print(AVS_PRINT_INFO, L"\nSMMU:\n Major Rev:%d\n Base Address:0x%x\n", block->data.smmu.arch_major_rev, block->data.smmu.base);
+      sbsa_print(AVS_PRINT_INFO, L"\nSMMU:\n Major Rev:%d\n Base Address:0x%x\n",
+                 block->data.smmu.arch_major_rev, block->data.smmu.base);
+      break;
+      case IOVIRT_NODE_PMCG:
+      sbsa_print(AVS_PRINT_INFO, L"\nPMCG:\n Base:0x%x\n Overflow GSIV:0x%x\n Node Reference:0x%x\n",
+                 block->data.pmcg.base, block->data.pmcg.overflow_gsiv, block->data.pmcg.node_ref);
       break;
   }
   sbsa_print(AVS_PRINT_INFO, L"Number of ID Mappings:%d\n", block->num_data_map);
@@ -94,6 +99,7 @@ dump_iort_table(IOVIRT_INFO_TABLE *iovirt)
 {
   UINT32 i;
   IOVIRT_BLOCK *block = &iovirt->blocks[0];
+  sbsa_print(AVS_PRINT_INFO, L"Number of IOVIRT blocks = %d\n", iovirt->num_blocks);
   for(i = 0; i < iovirt->num_blocks; i++, block = IOVIRT_NEXT_BLOCK(block))
     dump_block(block);
 }
@@ -217,6 +223,10 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt
   NODE_DATA *data = &((*block)->data);
   VOID *node_data = &(iort_node->node_data[0]);
 
+  sbsa_print(AVS_PRINT_INFO, L"IORT node offset:%x, type: %d\n", (UINT8*)iort_node - (UINT8*)iort, iort_node->type);
+
+  SetMem(data, 0, sizeof(NODE_DATA));
+
   /* Populate the fields that are independent of node type */
   (*block)->type = iort_node->type;
   (*block)->num_data_map = iort_node->mapping_count;
@@ -252,18 +262,28 @@ iort_add_block(IORT_TABLE *iort, IORT_NODE *iort_node, IOVIRT_INFO_TABLE *IoVirt
       (*data).smmu.arch_major_rev = 3;
       count = &IoVirtTable->num_smmus;
       break;
+    case IOVIRT_NODE_PMCG:
+      (*data).pmcg.base = ((IORT_PMCG *)node_data)->base_address;
+      (*data).pmcg.overflow_gsiv = ((IORT_PMCG *)node_data)->overflow_interrupt_gsiv;
+      (*data).pmcg.node_ref = ((IORT_PMCG *)node_data)->node_reference;
+      next_block = ADD_PTR(IOVIRT_BLOCK, data_map, (*block)->num_data_map * sizeof(NODE_DATA_MAP));
+      offset = iort_add_block(iort, ADD_PTR(IORT_NODE, iort, (*data).pmcg.node_ref),
+                              IoVirtTable, &next_block);
+      (*data).pmcg.node_ref = offset;
+      count = &IoVirtTable->num_pmcgs;
+      break;
     default:
        sbsa_print(AVS_PRINT_ERR, L"Invalid IORT node type\n");
        return (UINT32) -1;
   }
 
+  (*block)->flags = 0;
   /* Have we already added this block? */
   /* If so, return the block offset */
   offset = find_block(*block, IoVirtTable);
   if(offset)
     return offset;
 
-  (*block)->flags = 0;
   /* Calculate the position where next block should be added */
   next_block = ADD_PTR(IOVIRT_BLOCK, data_map, (*block)->num_data_map * sizeof(NODE_DATA_MAP));
   if(iort_node->type == IOVIRT_NODE_SMMU) {
@@ -326,6 +346,7 @@ pal_iovirt_create_info_table(IOVIRT_INFO_TABLE *IoVirtTable)
   IoVirtTable->num_pci_rcs = 0;
   IoVirtTable->num_named_components = 0;
   IoVirtTable->num_its_groups = 0;
+  IoVirtTable->num_pmcgs = 0;
 
   if(PLATFORM_OVERRIDE_SMMU_BASE) {
     iovirt_create_override_table(IoVirtTable);

platform/pal_uefi/src/pal_pcie.c

@@ -123,10 +123,11 @@ pal_pcie_create_info_table(PCIE_INFO_TABLE *PcieTable)
 
     @param   Bdf      - BDF value for the device
     @param   offset - Register offset within a device PCIe config space
-    @return  32 bit value at offset from ECAM base of the device specified by BDF value
+    @param   *data - 32 bit value at offset from ECAM base of the device specified by BDF value
+    @return  success/failure
 **/
 UINT32
-pal_pcie_read_cfg(UINT32 Bdf, UINT32 offset)
+pal_pcie_read_cfg(UINT32 Bdf, UINT32 offset, UINT32 *data)
 {
 
   EFI_STATUS                    Status;
@@ -135,15 +136,16 @@ pal_pcie_read_cfg(UINT32 Bdf, UINT32 offset)
   EFI_HANDLE                    *HandleBuffer;
   UINTN                         Seg, Bus, Dev, Func;
   UINT32                        Index;
-  UINT32                        InputBus, InputDev, InputFunc, Data;
+  UINT32                        InputSeg, InputBus, InputDev, InputFunc;
 
 
   Status = gBS->LocateHandleBuffer (ByProtocol, &gEfiPciIoProtocolGuid, NULL, &HandleCount, &HandleBuffer);
   if (EFI_ERROR (Status)) {
     sbsa_print(AVS_PRINT_INFO,L"No PCI devices found in the system\n");
-    return EFI_SUCCESS;
+    return PCIE_READ_ERR;
   }
 
+  InputSeg = PCIE_EXTRACT_BDF_SEG(Bdf);
   InputBus = PCIE_EXTRACT_BDF_BUS(Bdf);
   InputDev = PCIE_EXTRACT_BDF_DEV(Bdf);
   InputFunc = PCIE_EXTRACT_BDF_FUNC(Bdf);
@@ -152,13 +154,14 @@ pal_pcie_read_cfg(UINT32 Bdf, UINT32 offset)
     Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID **)&Pci);
     if (!EFI_ERROR (Status)) {
       Pci->GetLocation (Pci, &Seg, &Bus, &Dev, &Func);
-      if (InputBus == Bus && InputDev == Dev && InputFunc == Func) {
-          Status = Pci->Pci.Read (Pci, EfiPciIoWidthUint32, offset, 1, &Data);
+      if (InputSeg == Seg && InputBus == Bus && InputDev == Dev && InputFunc == Func) {
+          Status = Pci->Pci.Read (Pci, EfiPciIoWidthUint32, offset, 1, data);
           if (!EFI_ERROR (Status))
-            return Data;
-          break;
+            return 0;
+          else
+            return PCIE_READ_ERR;
       }
     }
   }
-  return 0;
+  return PCIE_READ_ERR;
 }

test_pool/gic/test_g002.c

@@ -35,6 +35,12 @@ payload()
   num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
 
   if (num_ecam != 0) {
+      data = val_gic_get_info(GIC_INFO_VERSION);
+      if (data < 2) {
+          val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
+          return;
+      }
+
       data = val_gic_get_info(GIC_INFO_NUM_ITS);
 
       if (data == 0) {

test_pool/gic/test_g003.c

@@ -30,6 +30,12 @@ payload()
   uint32_t data;
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
+  data = val_gic_get_info(GIC_INFO_VERSION);
+  if (data < 3) {
+     val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
+     return;
+  }
+
   data = val_gic_get_info(GIC_INFO_SEC_STATES);
 
   if (data != 0)

test_pool/gic/test_g004.c

@@ -53,6 +53,12 @@ payload()
   uint32_t timeout = 0x100000;
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
+  data = val_gic_get_info(GIC_INFO_VERSION);
+  if (data < 3) {
+     val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
+     return;
+  }
+
   val_gic_install_isr(int_id, isr);
 
   // Write to GIC registers which will generate Maintenance interrupt

test_pool/io_virt/test_i001.c

@@ -35,7 +35,7 @@ payload()
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
 
   if (num_smmu == 0) {
-      val_print(AVS_PRINT_ERR, "\n    No SMMU Controllers are discovered ", 0);
+      val_print(AVS_PRINT_ERR, "\n       No SMMU Controllers are discovered ", 0);
       val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
       return;
   }

test_pool/io_virt/test_i002.c

@@ -34,7 +34,7 @@ payload()
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
 
   if (num_smmu == 0) {
-      val_print(AVS_PRINT_ERR, "\n    No SMMU Controllers are discovered ", 0);
+      val_print(AVS_PRINT_ERR, "\n       No SMMU Controllers are discovered ", 0);
       val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
       return;
   }

test_pool/io_virt/test_i003.c

@@ -34,7 +34,7 @@ payload()
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
 
   if (num_smmu == 0) {
-      val_print(AVS_PRINT_ERR, "\n\t No SMMU Controllers are discovered ", 0);
+      val_print(AVS_PRINT_ERR, "\n       No SMMU Controllers are discovered ", 0);
       val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
       return;
   }

test_pool/io_virt/test_i004.c

@@ -35,22 +35,22 @@ payload()
   data = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
 
   if (data == 0) {
-      val_print(AVS_PRINT_WARN, "\n      PCIe Subsystem not  discovered        ", 0);
+      val_print(AVS_PRINT_WARN, "\n       PCIe Subsystem not  discovered   ", 0);
       val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
       return;
   }
 
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
 
   if (num_smmu == 0) {
-      val_print(AVS_PRINT_ERR, "\n      No SMMU Controllers are discovered ", 0);
+      val_print(AVS_PRINT_ERR, "\n       No SMMU Controllers are discovered ", 0);
       val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
       return;
   }
 
   while (num_smmu--) {
       if (val_smmu_get_info(SMMU_CTRL_ARCH_MAJOR_REV, num_smmu) == 2) {
-          val_print(AVS_PRINT_WARN, "\n        Not valid for SMMU v2           ", 0);
+          val_print(AVS_PRINT_WARN, "\n       Not valid for SMMU v2           ", 0);
           val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
           return;
       }

test_pool/io_virt/test_i005.c

@@ -32,7 +32,7 @@ payload()
   num_smmu = val_smmu_get_info(SMMU_NUM_CTRL, 0);
 
   if (num_smmu == 0) {
-      val_print(AVS_PRINT_ERR, "\n      No SMMU Controllers are discovered ", 0);
+      val_print(AVS_PRINT_ERR, "\n       No SMMU Controllers are discovered ", 0);
       val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 3));
       return;
   }

test_pool/io_virt/test_i006.c

@@ -20,7 +20,7 @@
 #include "val/include/sbsa_avs_iovirt.h"
 
 #define TEST_NUM   (AVS_SMMU_TEST_NUM_BASE + 6)
-#define TEST_DESC  "Unique stream id for each req id  "
+#define TEST_DESC  "Unique stream id for each req id   "
 
 static
 void

test_pool/pcie/test_p003.c

@@ -27,12 +27,13 @@ void
 payload(void)
 {
 
-  uint64_t data;
+  uint32_t data;
   uint32_t num_ecam;
   uint64_t ecam_base;
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
   uint32_t bdf = 0;
   uint32_t bus, segment;
+  uint32_t ret;
 
   num_ecam = val_pcie_get_info(PCIE_INFO_NUM_ECAM, 0);
 
@@ -56,19 +57,19 @@ payload(void)
       bus = val_pcie_get_info(PCIE_INFO_START_BUS, num_ecam);
 
       bdf = PCIE_CREATE_BDF(segment, bus, 0, 0);
-      data = val_pcie_read_cfg(bdf, 0);
+      ret = val_pcie_read_cfg(bdf, 0, &data);
 
       //If this is really PCIe CFG space, Device ID and Vendor ID cannot be 0 or 0xFFFF
-      if ((data == 0) || ((data & 0xFFFF) == 0xFFFF)) {
+      if (ret == PCIE_READ_ERR || (data == 0) || ((data & 0xFFFF) == 0xFFFF)) {
           val_print(AVS_PRINT_ERR, "\n      Incorrect data at ECAM Base %4x    ", data);
           val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01));
           return;
       }
 
-      data = val_pcie_read_cfg(bdf, 0xC);
+      ret = val_pcie_read_cfg(bdf, 0xC, &data);
 
       //If this really is PCIe CFG, Header type[6:0] must be 01 or 00
-      if (((data >> 16) & 0x7F) > 01) {
+      if (ret == PCIE_READ_ERR || ((data >> 16) & 0x7F) > 01) {
           val_print(AVS_PRINT_ERR, "\n      Incorrect PCIe CFG Hdr type %4x    ", data);
           val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02));
           return;

test_pool/pcie/test_p009.c

@@ -109,10 +109,6 @@ payload (void)
           }
           clean_msi_list (dev_mvec);
         }
-      } else {
-        val_print (AVS_STATUS_ERR, "\n       Failed to get address of PCI device", 0);
-        val_set_status (index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 1));
-        status = 1;
       }
     }
     count--;