Merge pull request #10 from ARM-software/master

Merging Bug fixes done after Beta release.

platform/pal_uefi/src/AArch64/AvsTestInfra.S

@@ -18,13 +18,10 @@
 .text
 .align 3
 
-GCC_ASM_EXPORT(UpdateElr)
 GCC_ASM_EXPORT(DataCacheCleanInvalidateVA)
 GCC_ASM_EXPORT(DataCacheInvalidateVA)
 GCC_ASM_EXPORT(DataCacheCleanVA)
 
-#define FP_CONTEXT_SIZE   0x200
-
 ASM_PFX(DataCacheCleanInvalidateVA):
   dc  civac, x0
   dsb sy
@@ -43,20 +40,3 @@ ASM_PFX(DataCacheInvalidateVA):
   isb
   ret
 
-ASM_PFX(UpdateElr):
-  // This function returns the stacked address of ELR in UEFI exception path
-  // The sequence of context save before the control is handed over
-  // to test-specific handler includes:
-  // 1. General Purpose registers, occupying 0x100 bytes (32*8)
-  // 2. Floating Point registers, occupying 0x200 bytes (32*16)
-  // 3. System Registers, occupying 0x30 (6*8) - ELR,SPSR,FPSR,ESR,FAR
-  // X28 points to start of FP context, and an offset of 0x200 should be
-  // added to make it point to system register context and
-  // ELR is the first register stacked there.
-  // For more info on the calculation of stacked address, please refer following file:
-  // <EDK2_PATH>/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S
-
-  add   x1, x28, #FP_CONTEXT_SIZE
-  str   x0, [x1]    // Update the stacked location with user address
-
-  ret

platform/pal_uefi/src/pal_pe.c

@@ -74,18 +74,19 @@ PalGetMaxMpidr()
 VOID
 PalAllocateSecondaryStack(UINT64 mpidr)
 {
-  EFI_STATUS Status, NumPe, Aff0, Aff1, Aff2, Aff3;
+  EFI_STATUS Status;
+  UINT32 MaxPe, Aff0, Aff1, Aff2, Aff3;
 
   Aff0 = ((mpidr & 0x00000000ff) >>  0);
   Aff1 = ((mpidr & 0x000000ff00) >>  8);
   Aff2 = ((mpidr & 0x0000ff0000) >> 16);
   Aff3 = ((mpidr & 0xff00000000) >> 32);
 
-  NumPe = ((Aff3+1) * (Aff2+1) * (Aff1+1) * (Aff0+1));
+  MaxPe = ((Aff3+1) * (Aff2+1) * (Aff1+1) * (Aff0+1));
 
   if (gSecondaryPeStack == NULL) {
       Status = gBS->AllocatePool ( EfiBootServicesData,
-                    (NumPe * SIZE_STACK_SECONDARY_PE),
+                    (MaxPe * SIZE_STACK_SECONDARY_PE),
                     (VOID **) &gSecondaryPeStack);
       if (EFI_ERROR(Status)) {
           Print(L"\n FATAL - Allocation for Seconday stack failed %x \n", Status);
@@ -153,6 +154,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable)
 
   gMpidrMax = MpidrAff0Max | MpidrAff1Max | MpidrAff2Max | MpidrAff3Max;
   pal_pe_data_cache_ops_by_va((UINT64)PeTable, CLEAN_AND_INVALIDATE);
+  pal_pe_data_cache_ops_by_va((UINT64)&gMpidrMax, CLEAN_AND_INVALIDATE);
   PalAllocateSecondaryStack(gMpidrMax);
 
 }
@@ -167,7 +169,7 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable)
   @return status of the API
 **/
 UINT32
-pal_pe_install_esr(UINT32 ExceptionType,  VOID (*esr)())
+pal_pe_install_esr(UINT32 ExceptionType,  VOID (*esr)(UINT64, VOID *))
 {
 
   EFI_STATUS  Status;
@@ -193,7 +195,7 @@ pal_pe_install_esr(UINT32 ExceptionType,  VOID (*esr)())
   //
   // Register to receive interrupts
   //
-  Status = Cpu->RegisterInterruptHandler (Cpu, ExceptionType, esr);
+  Status = Cpu->RegisterInterruptHandler (Cpu, ExceptionType, (EFI_CPU_INTERRUPT_HANDLER)esr);
   if (EFI_ERROR (Status)) {
     return Status;
   }
@@ -242,13 +244,9 @@ pal_pe_execute_payload(ARM_SMC_ARGS *ArmSmcArgs)
 }
 
 VOID
-UpdateElr(UINT64 offset);
-
-
-VOID
-pal_pe_update_elr(UINT64 offset)
+pal_pe_update_elr(VOID *context, UINT64 offset)
 {
-  UpdateElr(offset);
+  ((EFI_SYSTEM_CONTEXT_AARCH64*)context)->ELR = offset;
 }
 
 VOID

platform/pal_uefi/src/pal_peripherals.c

@@ -65,14 +65,14 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
           per_info++;
        }
        StartBdf = incrementBusDev(DeviceBdf);
-       
+
   } while (DeviceBdf != 0);
 
 
   StartBdf = 0;
   /* check for any SATA Controllers */
   do {
-  
+
        DeviceBdf = palPcieGetBdf(SATA_CLASSCODE, StartBdf);
        if (DeviceBdf != 0) {
           per_info->type  = PERIPHERAL_TYPE_SATA;
@@ -105,7 +105,7 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
     per_info->type  = PERIPHERAL_TYPE_UART;
     per_info++;
   }
-  
+
   per_info->type = 0xFF; //indicate end of table
 
 }
@@ -237,7 +237,7 @@ pal_memory_ioremap(VOID *ptr, UINT32 size, UINT32 attr)
 
 
 VOID
-pal_memory_unmap(void *ptr)
+pal_memory_unmap(VOID *ptr)
 {
 
   return;

platform/pal_uefi/src/pal_timer_wd.c

@@ -33,7 +33,7 @@ pal_get_gtdt_ptr();
 
 /* Information about only one timer can be mentioned as an Override */
 static
-void
+VOID
 pal_timer_platform_override(TIMER_INFO_TABLE *TimerTable)
 {
   if (PLATFORM_OVERRIDE_PLATFORM_TIMER) {
@@ -63,7 +63,7 @@ pal_timer_platform_override(TIMER_INFO_TABLE *TimerTable)
 
   @return  None
 **/
-void
+VOID
 pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable)
 {
   EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE       *Entry;
@@ -123,10 +123,10 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable)
         GtEntry->GtCntEl0Base[i] = GtBlockTimer->CntEL0BaseX;
         GtEntry->gsiv[i]         = GtBlockTimer->GTxPhysicalTimerGSIV;
         GtEntry->virt_gsiv[i]    = GtBlockTimer->GTxVirtualTimerGSIV;
-        GtEntry->flags[i]        = GtBlockTimer->GTxPhysicalTimerFlags | (GtBlockTimer->GTxVirtualTimerFlags << 8);
+        GtEntry->flags[i]        = GtBlockTimer->GTxPhysicalTimerFlags | (GtBlockTimer->GTxVirtualTimerFlags << 8) | (GtBlockTimer->GTxCommonFlags << 16);
         GtBlockTimer++;
+        TimerTable->header.num_platform_timer++;
       }
-      TimerTable->header.num_platform_timer++;
       GtEntry++;
     }
 
@@ -146,7 +146,7 @@ pal_timer_create_info_table(TIMER_INFO_TABLE *TimerTable)
 
 
 /* Only one watchdog information can be assigned as an override */
-void
+VOID
 pal_wd_platform_override(WD_INFO_TABLE *WdTable)
 {
 
@@ -171,7 +171,7 @@ pal_wd_platform_override(WD_INFO_TABLE *WdTable)
   @return  None
 **/
 
-void
+VOID
 pal_wd_create_info_table(WD_INFO_TABLE *WdTable)
 {
 

test_pool/pe/test_c001.c

@@ -21,37 +21,56 @@
 #define TEST_NUM   AVS_PE_TEST_NUM_BASE  +  1
 #define TEST_DESC  "Check for number of PE            "
 
-uint32_t
-c001_entry()
+static
+void
+payload()
 {
-  uint32_t num_pe = 0;
+  uint64_t num_of_pe = 0;
+  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
-  val_print(AVS_PRINT_ERR, "%4d : ", TEST_NUM);
-  val_print(AVS_PRINT_TEST, TEST_DESC, 0);
-  val_report_status(0, SBSA_AVS_START(g_sbsa_level, TEST_NUM));
-
-  num_pe = val_pe_get_num();
+  num_of_pe = val_pe_get_num();
 
   //
   //g_sbsa_level is set based on runtime input to the tool
   //
   if (g_sbsa_level < 2) {
-      if (num_pe > MAX_NUM_PE_LEVEL0) {
-          val_report_status(0, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01));
-          val_print(AVS_PRINT_ERR, "Number of PE is %d \n", num_pe);
-          return AVS_STATUS_FAIL;
+      if (num_of_pe > MAX_NUM_PE_LEVEL0) {
+          val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01));
+          val_print(AVS_PRINT_ERR, "Number of PE is %d \n", num_of_pe);
+          return;
       }
   } else {
-      if (num_pe > MAX_NUM_PE_LEVEL2) {
-          val_report_status(0, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01));
-          val_print(AVS_PRINT_ERR, "Number of PE is %d \n", num_pe);
-          return AVS_STATUS_FAIL;
+      if (num_of_pe > MAX_NUM_PE_LEVEL2) {
+          val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01));
+          val_print(AVS_PRINT_ERR, "Number of PE is %d \n", num_of_pe);
+          return;
       }
 
   }
 
-  val_report_status(0, RESULT_PASS(g_sbsa_level, TEST_NUM, 01));
+  val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01));
+
+  return;
+
+}
+
+uint32_t
+c001_entry()
+{
+
+  uint32_t status = AVS_STATUS_FAIL;  //default value
+  uint32_t num_pe = 1;
+
+  status = val_initialize_test(TEST_NUM, TEST_DESC, num_pe, g_sbsa_level);
+
+  /* This check is when user is forcing us to skip this test */
+  if (status != AVS_STATUS_SKIP)
+      val_run_test_payload(TEST_NUM, num_pe, payload, 0);
+
+  /* get the result from all PE and check for failure */
+  status = val_check_for_error(TEST_NUM, num_pe);
+
   val_report_status(0, SBSA_AVS_END(g_sbsa_level, TEST_NUM));
-  return AVS_STATUS_PASS;
 
+  return status;
 }

test_pool/pe/test_c002.c

@@ -28,8 +28,9 @@ payload()
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
   data = val_pe_reg_read(ID_AA64PFR0_EL1);
+  data = (data & 0xF00000) >> 20;
 
-  if ((data & 0xF00000) == 0) 
+  if ((data == 0x0) || (data == 0x1))
         val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01));
   else
         val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01));

test_pool/pe/test_c007.c

@@ -29,7 +29,7 @@ payload()
 
   data = val_pe_reg_read(ID_AA64ISAR0_EL1);
 
-  if (((data > 4) & 0xF) && ((data >> 8) & 0xF) && ((data >> 12) & 0xF))  //bits 7:4, 11:8, 15:12 must be non-zero
+  if (((data >> 4) & 0xF) && ((data >> 8) & 0xF) && ((data >> 12) & 0xF))  //bits 7:4, 11:8, 15:12 must be non-zero
 	val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01));
   else
 	val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01));

test_pool/pe/test_c011.c

@@ -27,7 +27,12 @@ void
 set_pmu_overflow()
 {
   uint64_t pmcr;
-
+
+  //Initializing the state of overflow status and interrupt request registers
+  val_pe_reg_write(PMINTENCLR_EL1, 0xFFFFFFFF);
+  val_pe_reg_write(PMOVSCLR_EL0, 0xFFFFFFFF);
+
+  //Sequence to generate PMUIRQ
   pmcr = val_pe_reg_read(PMCR_EL0);
   val_pe_reg_write(PMCR_EL0, pmcr|0x1);
 

test_pool/pe/test_c015.c

@@ -25,7 +25,7 @@
 #define RAS               1
 #define SPE               2
 #define LOR               3
-#define AA64              4
+#define AA32              4
 
 #define MASK_AA64MMFR0    0xF
 #define MASK_MIDR         0x00F0FFFF
@@ -61,23 +61,23 @@ reg_details reg_list[] = {
     {MIDR_EL1,         MASK_MIDR,      "MIDR_EL1"        , 0x0 },
     {VPIDR_EL2,        MASK_VPIDR,     "VPIDR_EL2"       , 0x0 },
     {CCSIDR_EL1,       MASK_CCSIDR,    "CCSIDR_EL1"      , 0x0 },
-    {ID_DFR0_EL1,      0x0,            "ID_DFR0_EL1"     , AA64},
-    {ID_ISAR0_EL1,     0x0,            "ID_ISAR0_EL1"    , AA64},
-    {ID_ISAR1_EL1,     0x0,            "ID_ISAR1_EL1"    , AA64},
-    {ID_ISAR2_EL1,     0x0,            "ID_ISAR2_EL1"    , AA64},
-    {ID_ISAR3_EL1,     0x0,            "ID_ISAR3_EL1"    , AA64},
-    {ID_ISAR4_EL1,     0x0,            "ID_ISAR4_EL1"    , AA64},
-    {ID_ISAR5_EL1,     0x0,            "ID_ISAR5_EL1"    , AA64},
-    {ID_MMFR0_EL1,     0x0,            "ID_MMFR0_EL1"    , AA64},
-    {ID_MMFR1_EL1,     0x0,            "ID_MMFR1_EL1"    , AA64},
-    {ID_MMFR2_EL1,     0x0,            "ID_MMFR2_EL1"    , AA64},
-    {ID_MMFR3_EL1,     0x0,            "ID_MMFR3_EL1"    , AA64},
-    {ID_MMFR4_EL1,     0x0,            "ID_MMFR4_EL1"    , AA64},
-    {ID_PFR0_EL1,      0x0,            "ID_PFR0_EL1"     , AA64},
-    {ID_PFR1_EL1,      0x0,            "ID_PFR1_EL1"     , AA64},
-    {MVFR0_EL1,        0x0,            "MVFR0_EL1"       , AA64},
-    {MVFR1_EL1,        0x0,            "MVFR1_EL1"       , AA64},
-    {MVFR2_EL1,        0x0,            "MVFR2_EL1"       , AA64},
+    {ID_DFR0_EL1,      0x0,            "ID_DFR0_EL1"     , AA32},
+    {ID_ISAR0_EL1,     0x0,            "ID_ISAR0_EL1"    , AA32},
+    {ID_ISAR1_EL1,     0x0,            "ID_ISAR1_EL1"    , AA32},
+    {ID_ISAR2_EL1,     0x0,            "ID_ISAR2_EL1"    , AA32},
+    {ID_ISAR3_EL1,     0x0,            "ID_ISAR3_EL1"    , AA32},
+    {ID_ISAR4_EL1,     0x0,            "ID_ISAR4_EL1"    , AA32},
+    {ID_ISAR5_EL1,     0x0,            "ID_ISAR5_EL1"    , AA32},
+    {ID_MMFR0_EL1,     0x0,            "ID_MMFR0_EL1"    , AA32},
+    {ID_MMFR1_EL1,     0x0,            "ID_MMFR1_EL1"    , AA32},
+    {ID_MMFR2_EL1,     0x0,            "ID_MMFR2_EL1"    , AA32},
+    {ID_MMFR3_EL1,     0x0,            "ID_MMFR3_EL1"    , AA32},
+    {ID_MMFR4_EL1,     0x0,            "ID_MMFR4_EL1"    , AA32},
+    {ID_PFR0_EL1,      0x0,            "ID_PFR0_EL1"     , AA32},
+    {ID_PFR1_EL1,      0x0,            "ID_PFR1_EL1"     , AA32},
+    {MVFR0_EL1,        0x0,            "MVFR0_EL1"       , AA32},
+    {MVFR1_EL1,        0x0,            "MVFR1_EL1"       , AA32},
+    {MVFR2_EL1,        0x0,            "MVFR2_EL1"       , AA32},
     {PMCEID0_EL0,      0x0,            "PMCEID0_EL0"     , 0x0 },
     {PMCEID1_EL0,      0x0,            "PMCEID1_EL0"     , 0x0 },
     {PMCR_EL0,         MASK_PMCR,      "PMCR_EL0"        , 0x0 },
@@ -128,7 +128,7 @@ return_reg_value(uint32_t reg, uint8_t dependency)
             return 0;
         break;
 
-    case AA64: // If the register is UNK in pure AArch64 implementation, then skip register check
+    case AA32: // If the register is UNK in pure AArch64 implementation, then skip register check
         temp = val_pe_reg_read(ID_AA64PFR0_EL1);
         temp = (temp & 1);
         if(temp == 0)

test_pool/peripherals/test_d002.c

@@ -39,7 +39,7 @@ payload()
   }
 
   while (count != 0) {
-      bdf = val_peripheral_get_info(USB_BDF, count - 1);
+      bdf = val_peripheral_get_info(SATA_BDF, count - 1);
       interface = val_pcie_read_cfg(bdf, 0x8);
       interface = (interface >> 8) & 0xFF;
       if (interface != 0x01) {

test_pool/peripherals/test_m001.c

@@ -35,12 +35,12 @@ payload();
 
 static
 void
-esr()
+esr(uint64_t interrupt_type, void *context)
 {
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
 
   /* Update the ELR to point to next instrcution */
-  val_pe_update_elr((uint64_t)branch_to_test);
+  val_pe_update_elr(context, (uint64_t)branch_to_test);
 
   val_print(AVS_PRINT_INFO, "\n       Received DAbort Exception ", 0);
   val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01));

test_pool/peripherals/test_m002.c

@@ -28,13 +28,13 @@ static void *branch_to_test;
 
 static
 void
-esr()
+esr(uint64_t interrupt_type, void *context)
 {
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
   uint64_t syndrome;
 
   /* Update the ELR to return to test specified address */
-  val_pe_update_elr((uint64_t)branch_to_test);
+  val_pe_update_elr(context, (uint64_t)branch_to_test);
 
   syndrome = val_pe_reg_read(ESR_EL2);
   syndrome &= 0x3F;    // Get the DFSC field from ESR