Merge pull request #77 from edhay/release

Updated for Release Version V2.3

README.md

@@ -17,7 +17,7 @@ A few tests are executed by running the SBSA ACS Linux application which in turn
 
 
 ## Release details
- - Code Quality: REL v2.2
+ - Code Quality: REL v2.3
  - The tests are written for version 5.0 of the SBSA specification.
  - The compliance suite is not a substitute for design verification.
  - To review the SBSA ACS logs, ARM licensees can contact ARM directly through their partner managers.

changelog.txt

@@ -1,3 +1,7 @@
+v19.09_REL2.3
+* SBSA: PCI Express Exerciser Enhancements
+* SBSA: EL1 Exception Level Support for QEMU Default Configurations
+
 v19.04_REL2.2
 
 * SBSA: Support for baremetal templates with documentation.

linux_app/sbsa-acs-app/include/sbsa_app.h

@@ -21,7 +21,7 @@
 
 
 #define SBSA_APP_VERSION_MAJOR  2
-#define SBSA_APP_VERSION_MINOR  2
+#define SBSA_APP_VERSION_MINOR  3
 
 #include "sbsa_drv_intf.h"
 

platform/pal_uefi/SbsaPalLib.inf

@@ -1,5 +1,5 @@
 ## @file
-# Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved.
+# Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved.
 #  SPDX-License-Identifier : Apache-2.0
 #
 # Licensed under the Apache License, Version 2.0 (the "License");
@@ -37,6 +37,8 @@
   src/pal_iovirt.c
   src/pal_pcie_enumeration.c
   src/pal_peripherals.c
+  src/pal_exerciser.c
+  src/pal_smmu.c
 
 [Packages]
   MdePkg/MdePkg.dec
@@ -62,6 +64,7 @@
   gHardwareInterruptProtocolGuid                ## CONSUMES
   gEfiCpuArchProtocolGuid                       ## CONSUMES
   gEfiPciIoProtocolGuid                         ## CONSUMES
+  gHardwareInterrupt2ProtocolGuid               ## CONSUMES
 
 [Guids]
   gEfiAcpi20TableGuid

platform/pal_uefi/include/pal_exerciser.h

@@ -0,0 +1,132 @@
+/** @file
+ * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved.
+ * SPDX-License-Identifier : Apache-2.0
+
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+**/
+
+#ifndef __PAL_EXERCISER_H__
+#define __PAL_EXERCISER_H__
+
+#define EXERCISER_CLASSCODE 0x010203
+#define MAX_ARRAY_SIZE 32
+#define TEST_REG_COUNT 10
+#define TEST_DDR_REGION_CNT 16
+
+typedef struct {
+    UINT64 buf[MAX_ARRAY_SIZE];
+} EXERCISER_INFO_BLOCK;
+
+typedef struct {
+    UINT32                  num_exerciser_cards;
+    EXERCISER_INFO_BLOCK    info[];  //Array of information blocks - per stimulus generation controller
+} EXERCISER_INFO_TABLE;
+
+typedef enum {
+    EXERCISER_NUM_CARDS = 0x1
+} EXERCISER_INFO_TYPE;
+
+typedef enum {
+    EDMA_NO_SUPPORT   = 0x0,
+    EDMA_COHERENT     = 0x1,
+    EDMA_NOT_COHERENT = 0x2,
+    EDMA_FROM_DEVICE  = 0x3,
+    EDMA_TO_DEVICE    = 0x4
+} EXERCISER_DMA_ATTR;
+
+typedef enum {
+    SNOOP_ATTRIBUTES = 0x1,
+    LEGACY_IRQ       = 0x2,
+    MSIX_ATTRIBUTES  = 0x3,
+    DMA_ATTRIBUTES   = 0x4,
+    P2P_ATTRIBUTES   = 0x5,
+    PASID_ATTRIBUTES = 0x6
+} EXERCISER_PARAM_TYPE;
+
+typedef enum {
+    EXERCISER_RESET = 0x1,
+    EXERCISER_ON    = 0x2,
+    EXERCISER_OFF   = 0x3,
+    EXERCISER_ERROR = 0x4
+} EXERCISER_STATE;
+
+typedef enum {
+    START_DMA     = 0x1,
+    GENERATE_MSI  = 0x2,
+    GENERATE_L_INTR = 0x3,  //Legacy interrupt
+    MEM_READ      = 0x4,
+    MEM_WRITE     = 0x5,
+    CLEAR_INTR    = 0x6,
+    PASID_TLP_START = 0x7,
+    PASID_TLP_STOP  = 0x8,
+    NO_SNOOP_CLEAR_TLP_START = 0x9,
+    NO_SNOOP_CLEAR_TLP_STOP  = 0xa
+} EXERCISER_OPS;
+
+typedef enum {
+    ACCESS_TYPE_RD = 0x0,
+    ACCESS_TYPE_RW = 0x1
+} ECAM_REG_ATTRIBUTE;
+
+struct ecam_reg_data {
+    UINT32 offset;    //Offset into 4096 bytes ecam config reg space
+    UINT32 attribute;
+    UINT32 value;
+};
+
+struct exerciser_data_cfg_space {
+    struct ecam_reg_data reg[TEST_REG_COUNT];
+};
+
+typedef enum {
+    DEVICE_nGnRnE = 0x0,
+    DEVICE_nGnRE  = 0x1,
+    DEVICE_nGRE   = 0x2,
+    DEVICE_GRE    = 0x3
+} ARM_DEVICE_MEM;
+
+typedef enum {
+    NORMAL_NC = 0x4,
+    NORMAL_WT = 0x5
+} ARM_NORMAL_MEM;
+
+typedef enum {
+    MMIO_PREFETCHABLE = 0x0,
+    MMIO_NON_PREFETCHABLE = 0x1
+} BAR_MEM_TYPE;
+
+struct exerciser_data_bar_space {
+    void *base_addr;
+    BAR_MEM_TYPE type;
+};
+
+typedef union exerciser_data {
+    struct exerciser_data_cfg_space cfg_space;
+    struct exerciser_data_bar_space bar_space;
+} exerciser_data_t;
+
+typedef enum {
+    EXERCISER_DATA_CFG_SPACE = 0x1,
+    EXERCISER_DATA_BAR0_SPACE = 0x2,
+} EXERCISER_DATA_TYPE;
+
+VOID pal_exerciser_create_info_table (EXERCISER_INFO_TABLE *ExerciserInfoTable);
+UINT32 pal_exerciser_get_info(EXERCISER_INFO_TYPE Type, UINT32 Instance);
+UINT32 pal_exerciser_set_param(EXERCISER_PARAM_TYPE Type, UINT64 Value1, UINT64 Value2, UINT32 Instance);
+UINT32 pal_exerciser_get_param(EXERCISER_PARAM_TYPE Type, UINT64 *Value1, UINT64 *Value2, UINT32 Instance);
+UINT32 pal_exerciser_set_state(EXERCISER_STATE State, UINT64 *Value, UINT32 Instance);
+UINT32 pal_exerciser_get_state(EXERCISER_STATE State, UINT64 *Value, UINT32 Instance);
+UINT32 pal_exerciser_ops(EXERCISER_OPS Ops, UINT64 Param, UINT32 Instance);
+UINT32 pal_exerciser_get_data(EXERCISER_DATA_TYPE Type, exerciser_data_t *Data, UINT32 Instance);
+
+#endif

platform/pal_uefi/include/pal_uefi.h

@@ -82,6 +82,14 @@ typedef enum {
   ENTRY_TYPE_GICITS
 }GIC_INFO_TYPE_e;
 
+/* Interrupt Trigger Type */
+typedef enum {
+  INTR_TRIGGER_INFO_LEVEL_LOW,
+  INTR_TRIGGER_INFO_LEVEL_HIGH,
+  INTR_TRIGGER_INFO_EDGE_FALLING,
+  INTR_TRIGGER_INFO_EDGE_RISING
+}INTR_TRIGGER_INFO_TYPE_e;
+
 /**
   @brief  structure instance for GIC entry
 **/
@@ -176,6 +184,9 @@ typedef struct {
   PCIE_INFO_BLOCK block[];
 }PCIE_INFO_TABLE;
 
+VOID *pal_pci_bdf_to_dev(UINT32 bdf);
+VOID pal_pci_read_config_byte(UINT32 bdf, UINT8 offset, UINT8 *data);
+
 /**
   @brief  Instance of SMMU INFO block
 **/
@@ -188,6 +199,7 @@ typedef struct {
   UINT32 segment;
   UINT32 ats_attr;
   UINT32 cca;             //Cache Coherency Attribute
+  UINT64 smmu_base;
 }IOVIRT_RC_INFO_BLOCK;
 
 typedef struct {
@@ -300,6 +312,42 @@ typedef struct {
   PERIPHERAL_INFO_BLOCK   info[]; ///< Array of Information blocks - instantiated for each peripheral
 }PERIPHERAL_INFO_TABLE;
 
+/**
+  @brief MSI(X) controllers info structure
+**/
+
+typedef struct {
+  UINT32         vector_upper_addr; ///< Bus Device Function
+  UINT32         vector_lower_addr; ///< Base Address of the controller
+  UINT32         vector_data;       ///< Base Address of the controller
+  UINT32         vector_control;    ///< IRQ to install an ISR
+  UINT32         vector_irq_base;   ///< Base IRQ for the vectors in the block
+  UINT32         vector_n_irqs;     ///< Number of irq vectors in the block
+  UINT32         vector_mapped_irq_base; ///< Mapped IRQ number base for this MSI
+}PERIPHERAL_VECTOR_BLOCK;
+
+typedef struct PERIPHERAL_VECTOR_LIST_STRUCT
+{
+  PERIPHERAL_VECTOR_BLOCK vector;
+  struct PERIPHERAL_VECTOR_LIST_STRUCT *next;
+}PERIPHERAL_VECTOR_LIST;
+
+UINT32 pal_get_msi_vectors (UINT32 seg, UINT32 bus, UINT32 dev, UINT32 fn, PERIPHERAL_VECTOR_LIST **mvector);
+
+#define LEGACY_PCI_IRQ_CNT 4  // Legacy PCI IRQ A, B, C. and D
+#define MAX_IRQ_CNT 0xFFFF    // This value is arbitrary and may have to be adjusted
+
+typedef struct {
+  UINT32  irq_list[MAX_IRQ_CNT];
+  UINT32  irq_count;
+} PERIFERAL_IRQ_LIST;
+
+typedef struct {
+  PERIFERAL_IRQ_LIST  legacy_irq_map[LEGACY_PCI_IRQ_CNT];
+} PERIPHERAL_IRQ_MAP;
+
+UINT32 pal_pcie_get_root_port_bdf(UINT32 *seg, UINT32 *bus, UINT32 *dev, UINT32 *func);
+
 /* Memory INFO table */
 typedef enum {
   MEMORY_TYPE_DEVICE = 0x1000,
@@ -328,4 +376,9 @@ typedef struct {
 
 VOID  pal_memory_create_info_table(MEMORY_INFO_TABLE *memoryInfoTable);
 
+VOID    *pal_mem_alloc(UINT32 size);
+VOID    *pal_mem_alloc_coherent(UINT32 bdf, UINT32 size, VOID *pa);
+VOID    pal_mem_free_coherent(UINT32 bdf, UINT32 size, VOID *va, VOID *pa);
+VOID    *pal_mem_virt_to_phys(VOID *va);
+
 #endif

platform/pal_uefi/include/sbsa_pcie_enum.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -36,4 +36,10 @@ palPcieGetBdf(UINT32 class_code, UINT32 start_busdev);
 UINT64
 palPcieGetBase(UINT32 bdf, UINT32 bar_index);
 
+VOID *
+pal_pci_bdf_to_dev(UINT32 bdf);
+
+VOID
+pal_pci_read_config_byte(UINT32 bdf, UINT8 offset, UINT8 *val);
+
 #endif