Merge remote-tracking branch 'origin/master' into release

README.md

@@ -5,19 +5,19 @@
 ## Server Base System Architecture
 **Server Base System Architecture** (SBSA) specification specifies a hardware system architecture based on the ARM 64-bit architecture. Server system software such as operating systems, hypervisors, and firmware rely on this. It addresses processing element features and key aspects of system architecture. 
 
-For more information, download the [SBSA specification](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029/index.html)
+For more information, download the [SBSA specification](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029b/index.html)
 
 
 ## SBSA - Architecture Compliance Suite
 
 SBSA **Architecture Compliance Suite** (ACS) is a collection of self-checking, portable C-based tests.
-This suite includes a set of examples of the invariant behaviours that are provided by the [SBSA](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029/index.html) specification, so that implementers can verify if these behaviours have been interpreted correctly.
+This suite includes a set of examples of the invariant behaviours that are provided by the [SBSA](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029b/index.html) specification, so that implementers can verify if these behaviours have been interpreted correctly.
 Most of the tests are executed from UEFI Shell by executing the SBSA UEFI shell application.
 A few tests are executed by running the SBSA ACS Linux application which in turn depends on the SBSA ACS Linux kernel module.
 
 
 ## Release details
- - Code Quality: REL v1.4
+ - Code Quality: REL v1.5
  - The tests are written for version 3.0 of the SBSA specification.
  - The compliance suite is not a substitute for design verification.
  - To review the SBSA ACS logs, ARM licensees can contact ARM directly through their partner managers.

linux_app/sbsa-acs-app/include/sbsa_app.h

@@ -20,7 +20,7 @@
 
 
 #define SBSA_APP_VERSION_MAJOR  1
-#define SBSA_APP_VERSION_MINOR  4
+#define SBSA_APP_VERSION_MINOR  5
 
 #include "sbsa_drv_intf.h"
 

test_pool/pcie/test_p007.c

@@ -26,35 +26,41 @@ void
 payload(void)
 {
 
-  uint32_t count = val_peripheral_get_info(NUM_SATA, 0);
+  uint32_t count = val_peripheral_get_info(NUM_ALL, 0);
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
   uint32_t data;
+  uint32_t dev_type;
+  uint64_t dev_bdf;
+  uint32_t status = 0;
 
   if (!count){
-      val_print(AVS_PRINT_WARN, "\n       Skipping because no SATA controller present ", 0);
       val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
       return;
   }
 
-  while (count != 0) {
-      data = val_peripheral_get_info(SATA_FLAGS, count - 1);
+  while (count > 0) {
+      count--;
+      dev_bdf = val_peripheral_get_info(ANY_BDF, count);
+      /* Check for pcie device */
+      if (!val_peripheral_is_pcie(dev_bdf))
+          continue;
+
+      dev_type = val_pcie_get_device_type(dev_bdf);
+      /* Skipping MSI check for type-1 and type-2 headers */
+      if ((!dev_type) || (dev_type > 1))
+          continue;
+
+      data = val_peripheral_get_info(ANY_FLAGS, count);
 
       if ((data & PER_FLAG_MSI_ENABLED) == 0) {
           val_print(AVS_STATUS_ERR, "\n       MSI should be enabled for a PCIe device ", 0);
           val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 01));
+          status = 1;
           break;
-      } else {
-          if (val_peripheral_get_info(SATA_GSIV, count - 1))
-              val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01));
-          else {
-              val_print(AVS_STATUS_ERR, "\n       IRQ not assigned to the Device ", 0);
-              val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02));
-              break;
-          }
       }
-      count--;
   }
-
+  if (!status)
+      val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01));
 }
 
 uint32_t

test_pool/pcie/test_p008.c

@@ -62,17 +62,20 @@ check_list_duplicates (PERIPHERAL_VECTOR_LIST *list_one, PERIPHERAL_VECTOR_LIST
 
   uint32_t fcount = 0;
   uint32_t scount = 0;
+  uint32_t irq_start1, irq_end1;
+  uint32_t irq_start2, irq_end2;
 
   flist_node = list_one;
   slist_node = list_two;
 
   while (flist_node != NULL) {
     while (slist_node != NULL) {
-      if ((flist_node->vector.vector_lower_addr == slist_node->vector.vector_lower_addr) &&
-          (flist_node->vector.vector_upper_addr == slist_node->vector.vector_upper_addr) &&
-          (flist_node->vector.vector_data == slist_node->vector.vector_data)) {
+      irq_start1 = flist_node->vector.vector_irq_base;
+      irq_end1 = flist_node->vector.vector_irq_base + flist_node->vector.vector_n_irqs - 1;
+      irq_start2 = slist_node->vector.vector_irq_base;
+      irq_end2 = slist_node->vector.vector_irq_base + slist_node->vector.vector_n_irqs - 1;
+      if (!(irq_end1 < irq_start2 || irq_start1 > irq_end2))
         return 1;
-      }
       slist_node = slist_node->next;
       scount++;
     }

test_pool/pcie/test_p013.c

@@ -60,8 +60,9 @@ payload (void)
       data = val_pcie_is_devicedma_64bit(dev_bdf);
       if (data == 0) {
           if(!val_pcie_is_device_behind_smmu(dev_bdf)) {
-              val_print (AVS_STATUS_ERR, "\n       The device with bdf=0x%x doesn't support 64 bit addressing", dev_bdf);
-              val_print (AVS_STATUS_ERR, "\n       and is not behind SMMU", 0);
+              val_print (AVS_STATUS_ERR, "\n       WARNING:The device with bdf=0x%x doesn't support 64 bit addressing", dev_bdf);
+              val_print (AVS_STATUS_ERR, "\n       and is not behind SMMU. Please install driver for this device and", 0);
+              val_print (AVS_STATUS_ERR, "\n       test again. If driver is already installed, this test has failed.", 0);
               val_print (AVS_STATUS_ERR, "\n       The device is of type = %d", dev_type);
               val_set_status (index, RESULT_FAIL (g_sbsa_level, TEST_NUM, 1));
               return;

test_pool/peripherals/test_d003.c

@@ -70,7 +70,7 @@ uart_enable_txintr()
 {
   uint32_t data;
 
-  /* unmask TX interrupt bit 5 in */
+  /* Enable TX interrupt by setting mask bit[5] in UARTIMSC */
   data = uart_reg_read(SBSA_UARTIMSC, WIDTH_BIT32);
   data = data | (1<<5);
   uart_reg_write(SBSA_UARTIMSC, WIDTH_BIT32, data);
@@ -81,7 +81,7 @@ uart_disable_txintr()
 {
   uint32_t data;
 
-  /* mask TX interrupt bit 5 in */
+  /* Disable TX interrupt by clearing mask bit[5] in UARTIMSC */
   data = uart_reg_read(SBSA_UARTIMSC, WIDTH_BIT32);
   data = data & (~(1<<5));
   uart_reg_write(SBSA_UARTIMSC, WIDTH_BIT32, data);
@@ -94,9 +94,10 @@ static
 void
 isr()
 {
+  uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
   uart_disable_txintr();
   val_print(AVS_PRINT_DEBUG, "\n      Received interrupt      ", 0);
-  val_set_status(0, RESULT_PASS(g_sbsa_level, TEST_NUM, 0x01));
+  val_set_status(index, RESULT_PASS(g_sbsa_level, TEST_NUM, 0x01));
   val_gic_end_of_interrupt(int_id);
 }
 
@@ -195,6 +196,7 @@ payload1()
 {
   uint32_t count = val_peripheral_get_info(NUM_UART, 0);
   uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
+  uint32_t timeout = TIMEOUT_MEDIUM;
 
   if (count == 0) {
       val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM2, 01));
@@ -211,10 +213,14 @@ payload1()
           val_set_status(index, RESULT_PENDING(g_sbsa_level, TEST_NUM2));
           val_gic_install_isr(int_id, isr);
           uart_enable_txintr();
-          val_print(g_print_level, "\n       Test Message                      ", 0);
-          if (IS_RESULT_PENDING(val_get_status(index))) {
+          val_print_raw(g_print_level, "\n       Test Message                      ", 0);
+
+          while ((--timeout > 0) && (IS_RESULT_PENDING(val_get_status(index))));
+
+          if (timeout == 0) {
               val_print(AVS_PRINT_ERR, "\n     Did not receive UART interrupt on %d  ", int_id);
               val_set_status(index, RESULT_FAIL(g_sbsa_level, TEST_NUM2, 02));
+              return;
           }
       } else {
           val_set_status(index, RESULT_SKIP(g_sbsa_level, TEST_NUM2, 01));

uefi_app/SbsaAvs.h

@@ -20,7 +20,7 @@
 
 
   #define SBSA_ACS_MAJOR_VER  1
-  #define SBSA_ACS_MINOR_VER  4
+  #define SBSA_ACS_MINOR_VER  5
 
   #define G_SBSA_LEVEL  3
   #define G_PRINT_LEVEL AVS_PRINT_TEST

val/include/pal_interface.h

@@ -363,6 +363,7 @@ typedef struct {
 }PERIPHERAL_INFO_TABLE;
 
 void  pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *per_info_table);
+uint32_t pal_peripheral_is_pcie(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn);
 
 /**
   @brief MSI(X) controllers info structure
@@ -374,6 +375,7 @@ typedef struct {
   uint32_t         vector_data;       ///< Base Address of the controller
   uint32_t         vector_control;    ///< IRQ to install an ISR
   uint32_t         vector_irq_base;   ///< Base IRQ for the vectors in the block
+  uint32_t         vector_n_irqs;     ///< Number of irq vectors in the block
 }PERIPHERAL_VECTOR_BLOCK;
 
 typedef struct PERIPHERAL_VECTOR_LIST_STRUCT

val/include/val_interface.h

@@ -238,6 +238,7 @@ void     val_peripheral_create_info_table(uint64_t *peripheral_info_table);
 void     val_peripheral_free_info_table(void);
 uint32_t val_peripheral_execute_tests(uint32_t level, uint32_t num_pe);
 uint64_t val_peripheral_get_info(PERIPHERAL_INFO_e info_type, uint32_t index);
+uint32_t val_peripheral_is_pcie(uint32_t bdf);
 
 /* Memory Tests APIs */
 typedef enum {

val/src/avs_pcie.c

@@ -201,7 +201,7 @@ val_pcie_execute_tests(uint32_t level, uint32_t num_pe)
   status |= p005_entry(num_pe);
   status |= p006_entry(num_pe);
   status |= p007_entry(num_pe);
-//test needs to be changed  status |= p008_entry(num_pe);
+  status |= p008_entry(num_pe);
   status |= p009_entry(num_pe);
   status |= p010_entry(num_pe);
   status |= p011_entry(num_pe);
@@ -368,7 +368,6 @@ val_pcie_is_devicedma_64bit(uint32_t bdf)
   return (pal_pcie_is_devicedma_64bit(seg, bus, dev, func));
 }
 
-
 /**
   @brief   This API returns the bdf of root port
   @param   bdf             - PCIe BUS/Device/Function

val/src/avs_peripherals.c

@@ -17,7 +17,7 @@
 #include "include/sbsa_avs_val.h"
 #include "include/sbsa_avs_peripherals.h"
 #include "include/sbsa_avs_common.h"
-
+#include "include/sbsa_avs_pcie.h"
 
 PERIPHERAL_INFO_TABLE  *g_peripheral_info_table;
 
@@ -226,3 +226,19 @@ val_peripheral_free_info_table()
   pal_mem_free((void *)g_peripheral_info_table);
 }
 
+/**
+  @brief   Check if PCI device is PCI Express capable
+           1. Caller       -  Test Suite
+  @param   bdf      - PCIe BUS/Device/Function
+  @return  1 -> PCIe capable  0 -> no PCIe capable
+**/
+uint32_t val_peripheral_is_pcie(uint32_t bdf)
+{
+  uint32_t seg  = PCIE_EXTRACT_BDF_SEG (bdf);
+  uint32_t bus  = PCIE_EXTRACT_BDF_BUS (bdf);
+  uint32_t dev  = PCIE_EXTRACT_BDF_DEV (bdf);
+  uint32_t func = PCIE_EXTRACT_BDF_FUNC (bdf);
+
+  return pal_peripheral_is_pcie(seg, bus, dev, func);
+}
+