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Merge remote-tracking branch 'origin/master' into release
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Sakar Arora committed Jan 23, 2019
2 parents e49b7b2 + 3d27d52 commit 36c1d4b
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8 changes: 4 additions & 4 deletions README.md
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## Server Base System Architecture
**Server Base System Architecture** (SBSA) specification specifies a hardware system architecture based on the ARM 64-bit architecture. Server system software such as operating systems, hypervisors, and firmware rely on this. It addresses processing element features and key aspects of system architecture.
**Server Base System Architecture** (SBSA) specification specifies a hardware system architecture based on the ARM 64-bit architecture. Server system software such as operating systems, hypervisors, and firmware rely on this. It addresses processing element features and key aspects of system architecture.

For more information, download the [SBSA specification](http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0029b/index.html)

Expand All @@ -17,7 +17,7 @@ A few tests are executed by running the SBSA ACS Linux application which in turn


## Release details
- Code Quality: REL v2.0
- Code Quality: REL v2.1
- The tests are written for version 5.0 of the SBSA specification.
- The compliance suite is not a substitute for design verification.
- To review the SBSA ACS logs, ARM licensees can contact ARM directly through their partner managers.
Expand All @@ -30,8 +30,8 @@ A few tests are executed by running the SBSA ACS Linux application which in turn
- To get the latest version of the code with bug fixes and new features, use the master branch.

## Additional reading
- For details on the SBSA ACS UEFI Shell Application, see [SBSA ACS User Guide](docs/SBSA_ACS_User_Guide.pdf).
- For details on the Design of the SBSA ACS, see [Validation Methodology Document](docs/SBSA_Val_Methodolgy.pdf).
- For details on the SBSA ACS UEFI Shell Application, see [SBSA ACS User Guide](docs/Arm_SBSA_Architecture_Compliance_User_Guide.pdf).
- For details on the Design of the SBSA ACS, see [Validation Methodology Document](docs/Arm_SBSA_Architecture_Compliance_Validation_Methodology.pdf).
- For information about the test coverage scenarios that are implemented in the current release of ACS and the scenarios that are planned for the future releases, see [Testcase checklist](docs/testcase-checklist.md).


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16 changes: 8 additions & 8 deletions docs/testcase-checklist.md
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Expand Up @@ -60,26 +60,26 @@
| 302 | Watchdog | L2+ | Watchdog Signal 0 is routed as an SPIor LPI to the GIC and usable as a EL2 interrupt | 4.3.8 | yes | UEFI App |
| 401 | PCIe | L1+ | Systems must map memory space to PCI Express configuration space, using the PCI Express Enhanced Configuration Access Mechanism (ECAM). Tests should be robust to ARI being implemented | 8.1 | yes | Linux driver |
| 402 | PCIe | L1+ | The base address of each ECAM region is discoverable from system firmware data | 8.1 | yes | Linux driver |
| 403 | PCIe | L1+ | PEs are able to access the ECAM region | 8.1 | yes | Linux driver |
| 404 | PCIe | L1+ | All systems must support mapping PCI Express memory space as either device memory or non-cacheable memory | 8.2 | yes | Linux driver |
| 404 | PCIe | L1+ | When PCI Express memory space is mapped as normal memory, the system must support unaligned accesses to that region. | 8.2 | yes | Linux driver |
| 403, 801 | PCIe | L1+ | PEs are able to access the ECAM region | 8.1 | yes | Linux driver |
| 404, 802 | PCIe | L1+ | All systems must support mapping PCI Express memory space as either device memory or non-cacheable memory | 8.2 | yes | Linux driver |
| 404, 802 | PCIe | L1+ | When PCI Express memory space is mapped as normal memory, the system must support unaligned accesses to that region. | 8.2 | yes | Linux driver |
| 405 | PCIe | L3+ | In systems that are compatible with level 3 or above of the SBSA, the addresses sent by PCI express devices must be presented to the memory system or SMMU unmodified | 8.3 | yes | Linux driver |
| 405 | PCIe | L0+ | In a system where the PCI express does not use an SMMU, the PCI express devices have the same view of physical memory as the PEs | 8.3 | yes | Linux driver |
| 405 | PCIe | L0+ | PCIe I/O Coherency Scenarios without System MMU are covered | 8.7.1 | yes | Linux driver |
| 405, 803 | PCIe | L0+ | PCIe I/O Coherency Scenarios without System MMU are covered | 8.7.1 | yes | Linux driver |
| 405 | PCIe | L1+ | PCIe I/O Coherency Scenarios with System MMU are covered | 8.7.2 | yes | Linux driver |
| 406 | PCIe | L0+ | In a system with a SMMU for PCI express there are no transformations to addresses being sent by PCI express devices before they are presented as an input address to the SMMU. | 8.3 | yes | Linux driver |
| 406 | PCIe | L3+ | the addresses sent by PCI express devices must be presented to the memory system or SMMU unmodified | 4.4.8 | yes | Linux driver |
| 407 | PCIe | L1+ | Support for Message Signaled Interrupts (MSI/MSI-X) is required for PCI Express devices. MSI and MSI-X are edge-triggered interrupts that are delivered as a memory write transaction | 8.4 | yes | Linux driver |
| 408 | PCIe | L1+ | each unique MSI(-X) shall trigger an interrupt with a unique ID and the MSI(-X) shall target GIC registers requiring no hardware specific software to service the interrupt | 8.4 | No | Linux driver |
| 408, 804 | PCIe | L1+ | each unique MSI(-X) shall trigger an interrupt with a unique ID and the MSI(-X) shall target GIC registers requiring no hardware specific software to service the interrupt | 8.4 | Yes | Linux driver |
| | PCIe | L1+ | Add GICv2/v3 support details | 8.4.1/2 | No | Linux driver |
| 409 | GICv3 | L2+ | All MSIs and MSI-x are mapped to LPI | 4.3.2 | yes | Linux driver |
| 410 | PCIe | L3+ | If the system supports PCIe PASID, then at least 16 bits of PASID must be supported | 8.11 | yes | Linux driver |
| 410, 805 | PCIe | L3+ | If the system supports PCIe PASID, then at least 16 bits of PASID must be supported | 8.11 | yes | Linux driver |
| 411 | PCIe | L0+ | The PCI Express root complex is in the same Inner Shareable domain as the PEs | 8.7 | yes | Linux driver |
| 412 | PCIe | L1+ | Each of the 4 legacy interrupt lines must be allocated a unique SPI ID and is programmed as level sensitive | 8.5 | yes | Linux driver |
| 412, 806 | PCIe | L1+ | Each of the 4 legacy interrupt lines must be allocated a unique SPI ID and is programmed as level sensitive | 8.5 | yes | Linux driver |
| 413 | MemoryMap | L3+ | All Non-secure on-chip masters in a base server system that are expected to be under the control of the OS or hypervisor must be capable of addressing all of the NS address space. If the master goes through a SMMU then it must be capable of addressing all of the NS address space when the SMMU is off. | 4.4.3 | yes | Linux driver |
| 413 | MemoryMap / PCIe | L3+ | Non-secure off-chip devices that cannot directly address all of the Non-secure address space must be placed behind a stage 1 System MMU compatible with the ARM SMMUv2 or SMMUv3 specification. that has an output address size large enough to address all of the Non-secure address space. | 4.4.3 | yes | Linux driver |
| 414 | Peripheral Subsystems | L3+ | Memory Attributes of DMA traffic are one of (1) Inner WB, Outer WB, Inner Shareable (2) Inner/Outer Non-Cacheable (3) Device TypeIO Coherent DMA is as per (1) Inner/Outer WB, Inner Shareable | 4.4.8 | yes | Linux driver |
| 415 | PCIe | L0+ | PCI Express transactions not marked as No_snoop accessing memory that the PE translation tables attribute as cacheable and shared are I/O Coherent with the PEs. | 8.7 | yes | Linux driver |
| 415, 807 | PCIe | L0+ | PCI Express transactions not marked as No_snoop accessing memory that the PE translation tables attribute as cacheable and shared are I/O Coherent with the PEs. | 8.7 | yes | Linux driver |
| 416 | PCIe | L4+ | For Non-prefetchable (NP) memory, type-1 headers only support 32bit address, systems complaint with SBSA level 4 or above must support 32bit programming of NP BARs on such endpoints | D.2 | yes | Linux driver |
| 504 | Watchdog | L1+ | Watchdog Signal 0 should be able to wakeup at least one PE from various low power states. Based off power states supported - this should be covered for 1 of N condition with some PEs in low power and from the lowest power stated where the Watchdog is ON. | 4.2.6 | yes | UEFI App |
| 504 | System counter and generic timer | L1+ | Unless all local PE timers are Always ON, a system timer based on architecture memory mapped generic timer view shall generate an SPI that wake the platform from states with semantics B,C,D,E,F,H,I | 4.2.3 | yes | UEFI App |
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5 changes: 2 additions & 3 deletions linux_app/sbsa-acs-app.bb
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Expand Up @@ -14,14 +14,13 @@ SRC_URI = "file://sbsa_app_main.c \
file://sbsa_drv_intf.c \
file://include/sbsa_drv_intf.h \
file://include/sbsa_app.h \
https://raw.githubusercontent.com/ARM-software/sbsa-acs/master/val/include/sbsa_avs_common.h \
file://include/sbsa_avs_common.h \
"
SRC_URI[md5sum] = "67ac822ba7b3a74c355c81663d8c7f21"

S = "${WORKDIR}"

do_compile() {
${CC} sbsa_app_main.c sbsa_app_pcie.c sbsa_drv_intf.c -o sbsa
${CC} sbsa_app_main.c sbsa_app_pcie.c sbsa_drv_intf.c -Iinclude -o sbsa
}

do_install() {
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2 changes: 1 addition & 1 deletion linux_app/sbsa-acs-app/Makefile
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Expand Up @@ -27,7 +27,7 @@ program_LIBRARY_DIRS :=
program_LIBRARIES :=
CC := $(CROSS_COMPILE)gcc

CPPFLAGS += $(foreach includedir,$(program_INCLUDE_DIRS),-I$(includedir)) -DTARGET_LINUX -g
CPPFLAGS += $(foreach includedir,$(program_INCLUDE_DIRS),-I$(includedir)) -DTARGET_LINUX -g -Werror
LDFLAGS += $(foreach librarydir,$(program_LIBRARY_DIRS),-L$(librarydir))
LDFLAGS += $(foreach library,$(program_LIBRARIES),-l$(library))

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5 changes: 4 additions & 1 deletion linux_app/sbsa-acs-app/include/sbsa_app.h
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Expand Up @@ -21,7 +21,7 @@


#define SBSA_APP_VERSION_MAJOR 2
#define SBSA_APP_VERSION_MINOR 0
#define SBSA_APP_VERSION_MINOR 1

#include "sbsa_drv_intf.h"

Expand All @@ -31,4 +31,7 @@ typedef unsigned char char8_t;
int
execute_tests_pcie(int num_pe, int level, unsigned int print_level);

int
execute_tests_exerciser(int num_pe, int level, unsigned int print_level);

#endif
1 change: 1 addition & 0 deletions linux_app/sbsa-acs-app/include/sbsa_drv_intf.h
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Expand Up @@ -25,6 +25,7 @@
#define SBSA_CREATE_INFO_TABLES 0x1000
#define SBSA_PCIE_EXECUTE_TEST 0x2000
#define SBSA_UPDATE_SKIP_LIST 0x3000
#define SBSA_EXERCISER_EXECUTE_TEST 0x4000
#define SBSA_FREE_INFO_TABLES 0x9000


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16 changes: 12 additions & 4 deletions linux_app/sbsa-acs-app/sbsa_app_main.c
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Expand Up @@ -64,6 +64,7 @@ main (int argc, char **argv)
int c = 0,i=0;
char *endptr, *pt;
int status;
int run_exerciser = 0;

struct option long_opt[] =
{
Expand All @@ -73,7 +74,7 @@ main (int argc, char **argv)
};

/* Process Command Line arguments */
while ((c = getopt_long(argc, argv, "hv:l:", long_opt, NULL)) != -1)
while ((c = getopt_long(argc, argv, "hv:l:e:", long_opt, NULL)) != -1)
{
switch (c)
{
Expand All @@ -95,6 +96,9 @@ main (int argc, char **argv)
pt = strtok(NULL, ",");
}
break;
case 'e':
run_exerciser = 1;
break;
case '?':
if (isprint (optopt))
fprintf (stderr, "Unknown option `-%c'.\n", optopt);
Expand Down Expand Up @@ -122,9 +126,13 @@ main (int argc, char **argv)
return 0;
}

printf("\n *** Starting PCIe tests *** \n");
execute_tests_pcie(1, g_sbsa_level, g_print_level);

if (run_exerciser) {
printf("\n *** Starting PCIe Exerciser tests *** \n");
execute_tests_exerciser(1, g_sbsa_level, g_print_level);
} else {
printf("\n *** Starting PCIe tests *** \n");
execute_tests_pcie(1, g_sbsa_level, g_print_level);
}

printf("\n *** SBSA tests complete *** \n\n");

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