Code improvements with additional compiler flags

- Code improvements to ensure no compiler warnings and errors. - Removal of unused variables. Signed-off-by: Srikar Josyula <[email protected]>
ARM-software · Nov 7, 2023 · 0712ef1 · 0712ef1
1 parent bfc80e2
commit 0712ef1
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Showing 38 changed files with 73 additions and 50 deletions.
diff --git a/test_pool/exerciser/operating_system/test_e001.c b/test_pool/exerciser/operating_system/test_e001.c
@@ -39,7 +39,7 @@ payload(void)
   exerciser_data_t e_data;
 
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
 
   while (instance-- != 0) {

diff --git a/test_pool/exerciser/operating_system/test_e002.c b/test_pool/exerciser/operating_system/test_e002.c
@@ -94,7 +94,7 @@ payload(void)
   mem_desc = &mem_desc_array[0];
   dram_buf_in_phys = 0;
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   /* Allocate an array to store base addresses of page tables allocated for
    * all exercisers

diff --git a/test_pool/exerciser/operating_system/test_e003.c b/test_pool/exerciser/operating_system/test_e003.c
@@ -100,7 +100,7 @@ payload(void)
   dram_buf_in_phys = 0;
 
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  num_exercisers = val_exerciser_get_info(EXERCISER_NUM_CARDS);
   num_smmus = val_iovirt_get_smmu_info(SMMU_NUM_CTRL, 0);
 
   /* Allocate an array to store base addresses of page tables allocated for

diff --git a/test_pool/exerciser/operating_system/test_e004.c b/test_pool/exerciser/operating_system/test_e004.c
@@ -279,7 +279,7 @@ cfgspace_transactions_order_check(void)
   uint64_t bdf_addr;
 
   /* Read the number of excerciser cards */
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0) {
 
@@ -335,7 +335,7 @@ barspace_transactions_order_check(void)
   uint32_t status;
 
   /* Read the number of excerciser cards */
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0) {
 

diff --git a/test_pool/exerciser/operating_system/test_e005.c b/test_pool/exerciser/operating_system/test_e005.c
@@ -152,7 +152,7 @@ barspace_transactions_order_check(void)
   uint32_t status;
 
   /* Read the number of excerciser cards */
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0) {
 

diff --git a/test_pool/exerciser/operating_system/test_e006.c b/test_pool/exerciser/operating_system/test_e006.c
@@ -288,7 +288,7 @@ payload(void)
   uint32_t dpc_cap_base = 0;
 
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0) {
 

diff --git a/test_pool/exerciser/operating_system/test_e007.c b/test_pool/exerciser/operating_system/test_e007.c
@@ -123,7 +123,7 @@ save_config_space(uint32_t rp_bdf)
          performed, all the devices connected below the RP is reset. This needs to be restored
          after SBR*/
       cfg_space_buf[tbl_index] = val_aligned_alloc(MEM_ALIGN_4K, PCIE_CFG_SIZE);
-      if (cfg_space_buf == NULL)
+      if (cfg_space_buf[tbl_index] == NULL)
       {
           val_print(AVS_PRINT_ERR, "\n       Memory allocation failed.", 0);
           val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, 02));
@@ -169,7 +169,7 @@ payload(void)
 
   fail_cnt = 0;
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0)
   {

diff --git a/test_pool/exerciser/operating_system/test_e008.c b/test_pool/exerciser/operating_system/test_e008.c
@@ -44,7 +44,7 @@ get_target_exer_bdf(uint32_t req_rp_bdf, uint32_t *tgt_e_bdf,
   uint32_t erp_ecam_index;
   uint32_t status;
 
-  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   while (instance-- != 0)
   {
@@ -172,7 +172,7 @@ payload(void)
   fail_cnt = 0;
   test_skip = 1;
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
-  req_instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  req_instance = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   status = val_pcie_p2p_support();
   /* Check If PCIe Hierarchy supports P2P. */

diff --git a/test_pool/mpam/operating_system/test_mpam002.c b/test_pool/mpam/operating_system/test_mpam002.c
@@ -28,7 +28,7 @@
 static void payload(void)
 {
     uint32_t llc_index;
-    uint32_t cache_identifier;
+    uint64_t cache_identifier;
     uint32_t msc_node_cnt;
     uint32_t rsrc_node_cnt;
     uint32_t msc_index, rsrc_index;

diff --git a/test_pool/mpam/operating_system/test_mpam006.c b/test_pool/mpam/operating_system/test_mpam006.c
@@ -37,7 +37,7 @@ static void payload(void)
     uint32_t msc_index;
     uint32_t rsrc_index;
     uint32_t llc_index;
-    uint32_t cache_identifier;
+    uint64_t cache_identifier;
     uint32_t cache_size;
     uint32_t max_pmg;
     uint32_t max_partid;

diff --git a/test_pool/pcie/operating_system/test_p033.c b/test_pool/pcie/operating_system/test_p033.c
@@ -34,7 +34,7 @@ payload(void)
   uint32_t pe_index;
   uint32_t tbl_index;
   uint32_t reg_value;
-  uint32_t max_payload_value;
+  int32_t max_payload_value;
   uint32_t dp_type;
   uint32_t test_fails;
   uint32_t test_skip = 1;

diff --git a/test_pool/smmu/operating_system/test_i012.c b/test_pool/smmu/operating_system/test_i012.c
@@ -32,7 +32,7 @@ payload()
 {
 
   uint64_t data;
-  uint64_t data_pe_endian;
+  uint64_t data_pe_endian = 0;
   uint32_t num_smmu;
   uint32_t index;
 

diff --git a/val/include/sbsa_avs_exerciser.h b/val/include/sbsa_avs_exerciser.h
@@ -109,7 +109,7 @@ typedef struct {
 
 void val_exerciser_create_info_table(void);
 uint32_t val_exerciser_init(uint32_t instance);
-uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance);
+uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type);
 uint32_t val_exerciser_set_param(EXERCISER_PARAM_TYPE type, uint64_t value1, uint64_t value2, uint32_t instance);
 uint32_t val_exerciser_get_param(EXERCISER_PARAM_TYPE type, uint64_t *value1, uint64_t *value2, uint32_t instance);
 uint32_t val_exerciser_set_state(EXERCISER_STATE state, uint64_t *value, uint32_t instance);

diff --git a/val/include/sbsa_avs_smmu.h b/val/include/sbsa_avs_smmu.h
@@ -44,7 +44,7 @@ uint32_t
 val_smmu_read_cfg(uint32_t offset, uint32_t index);
 
 uint64_t
-val_smmu_ops(SMMU_OPS_e ops, uint32_t index, void *param1, void *param2);
+val_smmu_ops(SMMU_OPS_e ops, void *param1, void *param2);
 
 uint32_t
 val_smmu_max_pasids(uint32_t smmu_index);

diff --git a/val/include/val_interface.h b/val/include/val_interface.h
@@ -54,6 +54,7 @@
 #define SINGLE_TEST_SENTINEL   10000
 #define SINGLE_MODULE_SENTINEL 10001
 
+typedef char char8_t;
 /* GENERIC VAL APIs */
 void val_allocate_shared_mem(void);
 void val_free_shared_mem(void);

diff --git a/val/src/avs_exerciser.c b/val/src/avs_exerciser.c
@@ -138,8 +138,9 @@ uint32_t val_get_exerciser_err_info(EXERCISER_ERROR_CODE type)
   @param   instance     - Stimulus hadrware instance number
   @return  value        - Information value for input type
 **/
-uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type, uint32_t instance)
+uint32_t val_exerciser_get_info(EXERCISER_INFO_TYPE type)
 {
+
     switch (type) {
     case EXERCISER_NUM_CARDS:
          return g_exerciser_info_table.num_exerciser;
@@ -312,7 +313,7 @@ val_exerciser_execute_tests(uint32_t level)
   val_print(AVS_PRINT_INFO, "\n      Starting Exerciser Setup\n", 0);
 
   val_exerciser_create_info_table();
-  num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
+  num_instances = val_exerciser_get_info(EXERCISER_NUM_CARDS);
 
   if (num_instances == 0) {
       val_print(AVS_PRINT_WARN, "\n     No Exerciser Devices Found, Skipping Exerciser tests...\n", 0);

diff --git a/val/src/avs_gic.c b/val/src/avs_gic.c
@@ -37,6 +37,7 @@ val_gic_execute_tests(uint32_t level, uint32_t num_pe)
 
   uint32_t status, i;
   uint32_t module_skip;
+  status = 0;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_GIC_TEST_NUM_BASE) {

diff --git a/val/src/avs_memory.c b/val/src/avs_memory.c
@@ -106,6 +106,7 @@ val_memory_execute_tests(uint32_t level, uint32_t num_pe)
 
   uint32_t status = 0;
   uint32_t i;
+  (void) level;
 
   for (i = 0 ; i < g_num_skip ; i++) {
       if (g_skip_test_num[i] == AVS_MEM_MAP_TEST_NUM_BASE) {

diff --git a/val/src/avs_mmu.c b/val/src/avs_mmu.c
@@ -228,7 +228,7 @@ uint32_t val_mmu_update_entry(uint64_t address, uint32_t size)
 **/
 static uint32_t log2_func(uint64_t value)
 {
-    int bit = 0;
+    uint32_t bit = 0;
 
     while (value != 0)
     {

diff --git a/val/src/avs_mpam.c b/val/src/avs_mpam.c
@@ -38,6 +38,7 @@ val_mpam_execute_tests(uint32_t level, uint32_t num_pe)
   uint32_t status = AVS_STATUS_FAIL, i;
   uint32_t skip_module;
   uint32_t msc_node_cnt;
+  (void) level;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_MPAM_TEST_NUM_BASE) {

diff --git a/val/src/avs_nist.c b/val/src/avs_nist.c
@@ -31,6 +31,7 @@ uint32_t
 val_nist_execute_tests(uint32_t level, uint32_t num_pe)
 {
   uint32_t status, i;
+  (void) level;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_NIST_TEST_NUM_BASE) {

diff --git a/val/src/avs_pcie.c b/val/src/avs_pcie.c
@@ -1242,6 +1242,8 @@ val_pcie_get_atomicop_requester_capable(uint32_t bdf)
 {
   /* TO DO */
   //return pal_pcie_get_atomicop_requester_capable(bdf);
+  (void) bdf;
+
   return 0;
 }
 

diff --git a/val/src/avs_pe.c b/val/src/avs_pe.c
@@ -42,6 +42,7 @@ extern ARM_SMC_ARGS g_smc_args;
 uint32_t
 val_pe_execute_tests(uint32_t level, uint32_t num_pe)
 {
+
   uint32_t status = AVS_STATUS_PASS, i;
 
   for (i = 0; i < g_num_skip; i++) {
@@ -242,11 +243,13 @@ val_pe_reg_read(uint32_t reg_id)
             return AA64ReadMair1();
           if (AA64ReadCurrentEL() == AARCH64_EL2)
             return AA64ReadMair2();
+          break;
       case TCR_ELx:
           if (AA64ReadCurrentEL() == AARCH64_EL1)
             return AA64ReadTcr1();
           if (AA64ReadCurrentEL() == AARCH64_EL2)
             return AA64ReadTcr2();
+          break;
       case ID_AA64ZFR0_EL1:
           return AA64ReadZfr0();
       default:

diff --git a/val/src/avs_pe_infra.c b/val/src/avs_pe_infra.c
@@ -378,6 +378,7 @@ val_pe_context_save(uint64_t sp, uint64_t elr)
 void
 val_pe_context_restore(uint64_t sp)
 {
+    (void) sp;
     sp = 0;
     *(uint64_t *)(g_stack_pointer+8) = g_ret_addr;
 }
@@ -408,7 +409,7 @@ void
 val_pe_default_esr(uint64_t interrupt_type, void *context)
 {
     uint32_t index = val_pe_get_index_mpid(val_pe_get_mpid());
-    val_print(AVS_PRINT_WARN, "\n        Unexpected exception occured", 0);
+    val_print(AVS_PRINT_WARN, "\n        Unexpected exception occured of type %d", interrupt_type);
 
 #ifndef TARGET_LINUX
     if (pal_target_is_bm()) {

diff --git a/val/src/avs_peripherals.c b/val/src/avs_peripherals.c
@@ -38,6 +38,8 @@ val_peripheral_execute_tests(uint32_t level, uint32_t num_pe)
 
   uint32_t status = AVS_STATUS_SKIP, i;
   uint32_t skip_module;
+  (void) level;
+  (void) num_pe;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_PER_TEST_NUM_BASE) {
@@ -54,7 +56,6 @@ val_peripheral_execute_tests(uint32_t level, uint32_t num_pe)
   }
 
   val_print_test_start("Peripheral");
-
   return status;
 }
 #endif

diff --git a/val/src/avs_pmu.c b/val/src/avs_pmu.c
@@ -37,6 +37,7 @@ val_pmu_execute_tests(uint32_t level, uint32_t num_pe)
   uint32_t status = AVS_STATUS_FAIL;
   uint32_t skip_module;
   uint32_t i, pmu_node_count;
+  (void) level;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_PMU_TEST_NUM_BASE) {

diff --git a/val/src/avs_ras.c b/val/src/avs_ras.c
@@ -34,9 +34,11 @@ static RAS2_INFO_TABLE *g_ras2_info_table;
 uint32_t
 val_ras_execute_tests(uint32_t level, uint32_t num_pe)
 {
+
   uint32_t status, i;
   uint32_t skip_module;
   uint64_t num_ras_nodes = 0;
+  (void) level;
 
   for (i = 0; i < g_num_skip; i++) {
       if (g_skip_test_num[i] == AVS_RAS_TEST_NUM_BASE) {
@@ -417,7 +419,7 @@ uint64_t
 val_ras_reg_read(uint32_t node_index, uint32_t reg, uint32_t err_rec_idx)
 {
   uint64_t base, value = INVALID_RAS_REG_VAL;
-  uint32_t start_rec_index, offset;
+  uint32_t start_rec_index, offset = 0;
   uint64_t num_err_recs, err_rec_impl_bitmap;
 
   start_rec_index = g_ras_info_table->node[node_index].intf_info.start_rec_index;
@@ -568,7 +570,7 @@ void
 val_ras_reg_write(uint32_t node_index, uint32_t reg, uint64_t write_data)
 {
   uint64_t base;
-  uint32_t rec_index, offset;
+  uint32_t rec_index, offset = 0;
 
   rec_index = g_ras_info_table->node[node_index].intf_info.start_rec_index;
 
@@ -768,7 +770,7 @@ uint32_t val_ras_check_err_record(uint32_t node_index, uint32_t error_type)
 {
   uint32_t status = AVS_STATUS_PASS;
   uint64_t err_status;
-  uint32_t err_type_mask;
+  uint32_t err_type_mask = 0;
 
   /* Loop for Wait */
   val_ras_wait_timeout(1);

diff --git a/val/src/avs_smmu.c b/val/src/avs_smmu.c
@@ -176,7 +176,7 @@ val_smmu_check_device_iova(uint32_t ctrl_index, addr_t dma_addr)
 
 
 uint64_t
-val_smmu_ops(SMMU_OPS_e ops, uint32_t smmu_index, void *param1, void *param2)
+val_smmu_ops(SMMU_OPS_e ops, void *param1, void *param2)
 {
 
   switch(ops)

diff --git a/val/src/avs_test_infra.c b/val/src/avs_test_infra.c
@@ -538,6 +538,7 @@ val_check_for_error(uint32_t test_num, uint32_t num_pe, char8_t *ruleid)
   uint32_t status = 0;
   uint32_t error_flag = 0;
   uint32_t my_index = val_pe_get_index_mpid(val_pe_get_mpid());
+  (void) test_num;
 
   /* this special case is needed when the Main PE is not the first entry
      of pe_info_table but num_pe is 1 for SOC tests */