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Merge pull request #219 from Sujana-M/master
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PCIe: pal_pcie_get_base() function bug fix
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@prasanth-pulla
prasanth-pulla authored Feb 11, 2022
2 parents 661b59e + 136091e commit 04e0de6
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Showing 3 changed files with 39 additions and 37 deletions.
4 changes: 3 additions & 1 deletion platform/pal_baremetal/include/pal_common_support.h
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/** @file
* Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2020-2021,2022 Arm Limited or its affiliates. All rights reserved.
* SPDX-License-Identifier : Apache-2.0
* Licensed under the Apache License, Version 2.0 (the "License");
Expand Down Expand Up @@ -61,6 +61,8 @@ extern uint32_t g_enable_module;
#define COMMAND_REG_OFFSET 0x04
#define REG_ACC_DATA 0x7

#define BAR_MASK 0xFFFFFFF0

/* Class Code Masks */
#define CC_SUB_MASK 0xFF /* Sub Class */
#define CC_BASE_MASK 0xFF /* Base Class */
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53 changes: 26 additions & 27 deletions platform/pal_baremetal/src/pal_pcie_enumeration.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/** @file
* Copyright (c) 2020-2021, Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2020-2022 Arm Limited or its affiliates. All rights reserved.
* SPDX-License-Identifier : Apache-2.0
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
Expand Down Expand Up @@ -158,8 +158,8 @@ get_resource_base_64(uint32_t bus, uint32_t dev, uint32_t func, uint64_t bar64_p
bar64_p_lower32_limit = bar64_p_lower32_limit - BAR_INCREMENT;
g_bar64_p_start = (g_bar64_p_start & MEM_BASE64_LIM_MASK) + BAR_INCREMENT;
pal_pci_cfg_write(bus, dev, func, PRE_FET_OFFSET, mem_bar_p);
pal_pci_cfg_write(bus, dev, func, PRE_FET_OFFSET+4, bar64_p_upper32_base);
pal_pci_cfg_write(bus, dev, func, PRE_FET_OFFSET+8, bar64_p_upper32_limit);
pal_pci_cfg_write(bus, dev, func, PRE_FET_OFFSET + 4, bar64_p_upper32_base);
pal_pci_cfg_write(bus, dev, func, PRE_FET_OFFSET + 8, bar64_p_upper32_limit);
}
}

Expand All @@ -173,7 +173,8 @@ void pal_pcie_program_bar_reg(uint32_t bus, uint32_t dev, uint32_t func)
{

uint64_t bar_size, bar_upper_bits;
uint32_t bar_reg_value, offset = BAR0_OFFSET;
uint32_t bar_reg_value, bar_lower_bits;
uint32_t offset = BAR0_OFFSET;
uint32_t np_bar_size = 0;
uint32_t p_bar_size = 0, p_bar64_size = 0;

Expand All @@ -185,15 +186,15 @@ void pal_pcie_program_bar_reg(uint32_t bus, uint32_t dev, uint32_t func)
{
if (BAR_REG(bar_reg_value) == BAR_64_BIT)
{
print(AVS_PRINT_INFO, "The BAR supports 64-bit address decoding capability \n", 0);
print(AVS_PRINT_INFO, "The BAR supports P_MEM 64-bit addr decoding capability\n", 0);

/** BAR supports 64-bit address therefore, write all 1's
* to BARn and BARn+1 and identify the size requested
**/
pal_pci_cfg_write(bus, dev, func, offset, 0xFFFFFFF0);
pal_pci_cfg_write(bus, dev, func, offset + 4, 0xFFFFFFFF);
pal_pci_cfg_read(bus, dev, func, offset, &bar_reg_value);
bar_size = bar_reg_value & 0xFFFFFFF0;
pal_pci_cfg_read(bus, dev, func, offset, &bar_lower_bits);
bar_size = bar_lower_bits & BAR_MASK;

pal_pci_cfg_read(bus, dev, func, offset + 4, &bar_reg_value);
bar_upper_bits = bar_reg_value;
Expand Down Expand Up @@ -236,16 +237,16 @@ void pal_pcie_program_bar_reg(uint32_t bus, uint32_t dev, uint32_t func)

}

if (BAR_REG(bar_reg_value) == BAR_32_BIT)
else
{
print(AVS_PRINT_INFO, "The BAR supports 32-bit address decoding capability\n", 0);
print(AVS_PRINT_INFO, "The BAR supports P_MEM 32-bit addr decoding capability\n", 0);

/**BAR supports 32-bit address. Write all 1's
* to BARn and identify the size requested
**/
pal_pci_cfg_write(bus, dev, func, offset, 0xFFFFFFF0);
pal_pci_cfg_read(bus, dev, func, offset, &bar_reg_value);
bar_reg_value = bar_reg_value & 0xFFFFFFF0;
pal_pci_cfg_read(bus, dev, func, offset, &bar_lower_bits);
bar_reg_value = bar_lower_bits & BAR_MASK;
bar_size = ~bar_reg_value + 1;

/**If BAR size is 0, then BAR not implemented, move to next BAR**/
Expand Down Expand Up @@ -286,22 +287,22 @@ void pal_pcie_program_bar_reg(uint32_t bus, uint32_t dev, uint32_t func)

else
{
print(AVS_PRINT_INFO, "The BAR supports 32-bit address decoding capability\n", 0);
print(AVS_PRINT_INFO, "The BAR supports NP_MEM 32-bit addr decoding capability\n", 0);

/**BAR supports 32-bit address. Write all 1's
* to BARn and identify the size requested
**/
pal_pci_cfg_write(bus, dev, func, offset, 0xFFFFFFF0);
pal_pci_cfg_read(bus, dev, func, offset, &bar_reg_value);
bar_reg_value = bar_reg_value & 0xFFFFFFF0;
pal_pci_cfg_read(bus, dev, func, offset, &bar_lower_bits);
bar_reg_value = bar_lower_bits & BAR_MASK;
bar_size = ~bar_reg_value + 1;

/**If BAR size is 0, then BAR not implemented, move to next BAR**/
if (bar_size == 0)
{
if (BAR_REG(bar_reg_value) == BAR_64_BIT)
if (BAR_REG(bar_lower_bits) == BAR_64_BIT)
offset = offset + 8;
if (BAR_REG(bar_reg_value) == BAR_32_BIT)
if (BAR_REG(bar_lower_bits) == BAR_32_BIT)
offset = offset + 4;
continue;
}
Expand Down Expand Up @@ -552,7 +553,8 @@ pal_pcie_get_base(uint32_t bdf, uint32_t bar_index)
{
uint32_t Bus, Dev, Func;
uint32_t offset;
uint32_t bar_reg_value;
uint32_t bar_reg_lower_value;
uint32_t bar_reg_upper_value;
uint64_t bar_value, bar_upper_bits;

Bus = PCIE_EXTRACT_BDF_BUS(bdf);
Expand All @@ -562,20 +564,17 @@ pal_pcie_get_base(uint32_t bdf, uint32_t bar_index)
offset = BAR0_OFFSET + (4*bar_index);


pal_pci_cfg_read(Bus, Dev, Func, offset, &bar_reg_value);
if (BAR_REG(bar_reg_value) == BAR_64_BIT)
pal_pci_cfg_read(Bus, Dev, Func, offset, &bar_reg_lower_value);

bar_value = bar_reg_lower_value & BAR_MASK;

if (BAR_REG(bar_reg_lower_value) == BAR_64_BIT)
{
bar_value = bar_reg_value & 0xFFFFFFF0;
pal_pci_cfg_read(Bus, Dev, Func, offset+4, &bar_reg_value);
bar_upper_bits = bar_reg_value;
pal_pci_cfg_read(Bus, Dev, Func, offset + 4, &bar_reg_upper_value);
bar_upper_bits = bar_reg_upper_value;
bar_value = bar_value | (bar_upper_bits << 32 );
}
if (BAR_REG(bar_reg_value) == BAR_32_BIT)
{
bar_value = bar_reg_value & 0xFFFFFFF0;


}
print(AVS_PRINT_INFO, "value read from BAR %x\n", bar_value);

return bar_value;
Expand Down
19 changes: 10 additions & 9 deletions test_pool/pcie/test_p005.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/** @file
* Copyright (c) 2016-2018, 2020-2021 Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2016-2018, 2020-2022 Arm Limited or its affiliates. All rights reserved.
* SPDX-License-Identifier : Apache-2.0
* Licensed under the Apache License, Version 2.0 (the "License");
Expand Down Expand Up @@ -50,6 +50,7 @@ payload(void)
uint32_t old_data;
uint32_t bdf;
uint32_t bar_reg_value;
uint32_t bar_reg_lower_value;
uint64_t bar_upper_bits;
uint32_t bar_value;
uint32_t bar_value_1;
Expand Down Expand Up @@ -125,8 +126,8 @@ payload(void)
*/
val_pcie_write_cfg(bdf, offset, 0xFFFFFFF0);
val_pcie_write_cfg(bdf, offset + 4, 0xFFFFFFFF);
val_pcie_read_cfg(bdf, offset, &bar_reg_value);
bar_size = bar_reg_value & 0xFFFFFFF0;
val_pcie_read_cfg(bdf, offset, &bar_reg_lower_value);
bar_size = bar_reg_lower_value & 0xFFFFFFF0;
val_pcie_read_cfg(bdf, offset + 4, &bar_reg_value);
bar_upper_bits = bar_reg_value;
bar_size = bar_size | (bar_upper_bits << 32 );
Expand All @@ -145,8 +146,8 @@ payload(void)
* to BARn and identify the size requested
*/
val_pcie_write_cfg(bdf, offset, 0xFFFFFFF0);
val_pcie_read_cfg(bdf, offset, &bar_reg_value);
bar_reg_value = bar_reg_value & 0xFFFFFFF0;
val_pcie_read_cfg(bdf, offset, &bar_reg_lower_value);
bar_reg_value = bar_reg_lower_value & 0xFFFFFFF0;
bar_size = ~bar_reg_value + 1;

/* Restore the original BAR value */
Expand Down Expand Up @@ -220,11 +221,11 @@ payload(void)
}

next_bar:
if (BAR_REG(bar_reg_value) == BAR_32_BIT)
offset=offset+4;
if (BAR_REG(bar_reg_lower_value) == BAR_32_BIT)
offset = offset + 4;

if (BAR_REG(bar_reg_value) == BAR_64_BIT)
offset=offset+8;
if (BAR_REG(bar_reg_lower_value) == BAR_64_BIT)
offset = offset + 8;

if (msa_en)
val_pcie_disable_msa(bdf);
Expand Down

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