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Alpha update - Bug Fixes for ACPI table parsing, memory allocation si…
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…ze for GIC table, Timer interrupt not received.

Adding new tests - system timer interrupt, GIC maintenance interrupt, secure mem access from non-secure mode.
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@prasanth-pulla
prasanth-pulla committed Jan 16, 2017
1 parent 4a1c2eb commit 02bb3d5
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21 changes: 11 additions & 10 deletions README.md
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Expand Up @@ -36,21 +36,22 @@ The present release implements a UEFI shell application to execute these tests f
### ACS Build steps

1. cd local_edk2_path
2. git clone https://github.com/ARM-software/sbsa-acs AppPkg/Applications/Sbsa
2. git clone https://github.com/ARM-software/sbsa-acs AppPkg/Applications/sbsa-acs
3. Add the following to the [LibraryClasses.common] section in ShellPkg/ShellPkg.dsc
- Add SbsaValLib|AppPkg/Applications/Sbsa/val/SbsaValLib.inf
- Add SbsaPalLib|AppPkg/Applications/Sbsa/platform/pal_uefi/SbsaPalLib.inf
4. Add AppPkg/Applications/Sbsa/uefi_app/SbsaAvs.inf in the [components] section of ShellPkg/ShellPkg.dsc
- Add SbsaValLib|AppPkg/Applications/sbsa-acs/val/SbsaValLib.inf
- Add SbsaPalLib|AppPkg/Applications/sbsa-acs/platform/pal_uefi/SbsaPalLib.inf
4. Add AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf in the [components] section of ShellPkg/ShellPkg.dsc

#### Linux
1. export GCC49_AARCH64_PREFIX= GCC5.3 toolchain path /bin/aarch64-linux-gnu-
1. export GCC49_AARCH64_PREFIX= "GCC5.3 toolchain path"/bin/aarch64-linux-gnu-
2. source edksetup.sh
3. make -C BaseTools/Source/C
4. source AppPkg/Applications/Sbsa/avsbuild.sh
4. source AppPkg/Applications/sbsa-acs/tools/scripts/avsbuild.sh

#### Windows
- To be added

1. Set the toolchain path to GCC53.
2. set up the environment for AARCH64 - edk2 build.
3. Build the Sbsa Shell application. example: build -a AARCH64 -t GCC49 -p ShellPkg/ShellPkg.dsc -m AppPkg/Applications/sbsa-acs/uefi_app/SbsaAvs.inf

### Build Output

Expand Down Expand Up @@ -98,8 +99,8 @@ On a system where a USB port is available and functional, follow the below steps
On an Emulation platform where secondary storage is not available.

1. Add the Sbsa.efi file as part of the UEFI FD file.
- Add Sbsa.efi as a binary to the UefiShellCommandLib
- Or add the SbsaAvsMain.inf to the UefiShellCommandLib.inf
- Add SbsaAvs.inf and the dependant VAL and PAL inf files to the Platform dsc and fdf files.
- Or add the SbsaAvs.inf and the dependant VAL and PAL inf files to the UefiShellCommandLib.inf
2. Build UEFI image including the UEFI Shell.
3. Boot the system to UEFI shell.
4. Run the executable “Sbsa.efi” to start the compliance tests.
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6 changes: 3 additions & 3 deletions docs/testcase-checklist.md
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Expand Up @@ -29,7 +29,7 @@
| 21 | GICv3 | L2+ | Interrupt controller shall conform to GICv3 specification | 4.3.2 | yes | |
| 22 | GICv3 | L2+ | If the base server system includes PCI Express then the GICv3 interrupt controller shall implement ITS and LPI | 4.3.2 | yes | |
| 23 | GIC | L3+ | The GICv3 interrupt controller shall support two Security states | 4.4.4 | yes | |
| | GICv2/3 | L2+ | GIC maintenance interrupt shall be wired as PPI 25 | 4.3.2.4 | no | |
| 24 | GICv2/3 | L2+ | GIC maintenance interrupt shall be wired as PPI 25 | 4.3.2.4 | yes | |
| 31 | System counter and generic timer | L0+ | Must run between 10Mhz and 400Mhz | 4.1.5 | yes | |
| 32 | System counter and generic timer | L1- | The local PE timer when expiring must generate a PPI when EL1 physical timer expires | 4.1.5 | yes | |
| 32 | System counter and generic timer | L2+ | The local PE timer when expiring must generate a PPI when EL1 physical timer expires, and PPI must be 30 | 4.1.54.3.2.1 | yes | |
Expand All @@ -51,7 +51,7 @@
| 52 | PCIe | L1+ | The base address of each ECAM region is discoverable from system firmware data | 8.1 | yes | |
| 53 | PCIe | L1+ | PEs are able to access the ECAM region | 8.1 | yes | |
| 54 | PCIe | L1+ | All systems must support mapping PCI Express memory space as either device memory or non-cacheable memory | 8.2 | yes | |
| 54 | PCIe | L1+ | When PCI Express memory space is mapped as normal memory, the system must support unaligned accesses to that region. | 8.2 | yes | |
| | PCIe | L1+ | When PCI Express memory space is mapped as normal memory, the system must support unaligned accesses to that region. | 8.2 | no | yes |
| 61 | IO Virtualisation | L0+ | SMMU if present must spport a 64KB granule, For L1- this would be an SMMUv1 for L2 SMMUv2, and | 4.1.4 | yes | |
| 62 | SMMU | L3+ | All the System MMUs in the system must the compliant with the same architecture version | 4.4.5 | yes | |
| 63 | SMMU | L3+ | If SMMUv3 is in use, The integration of the System MMUs is compliant with the specification in APPENDIX H: SMMUv3 Integration | 4.4.5Appendix H | yes | |
Expand Down Expand Up @@ -115,7 +115,7 @@
| | System counter and generic timer | L3+ | If the system includes a system wakeup timer, this memory-mapped timer must be mapped on to Non-secure address space | 4.4.6 | no | yes |
| | PCIe | L3+ | the addresses sent by PCI express devices must be presented to the memory system or SMMU unmodified | 4.4.8 | no | yes |
| | Peripheral Subsystems | L3+ | Memory Attributes of DMA traffic are one of (1) Inner WB, Outer WB, Inner Shareable (2) Inner/Outer Non-Cacheable (3) Device TypeIO Coherent DMA is as per (1) Inner/Outer WB, Inner Shareable | 4.4.8 | no | yes |
| | Peripheral Subsystems | L3 FW | Some memory is mapped in secure address space. The memory shall not be aliased in Non-secure address space | 4.5.1 | no | yes |
| 87 | Peripheral Subsystems | L3 FW | Some memory is mapped in secure address space. The memory shall not be aliased in Non-secure address space | 4.5.1 | yes | |
| | System counter and generic timer | L3 FW | A secure system wakeup timer is present and the interrupt is presented to GIC as a SPI | 4.5.2 | no | yes |
| 901 | Watchdog | L3 FW | The Watchdog Signal 1 is routed as a SPI to GIC and usable as an EL3 interrupt, directly targetting a single PE | 4.5.3 | no | yes |
| 904 | Watchdog | L3 FW | Secure Watchdog is implemented. Secure watchdog is not-aliased in non-secure address space. Signal 0 if secure watchdog is routed as an SPI and usable as an interrupt to EL3, directly targetting a single PE | 4.5.3 | no | yes |
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1 change: 0 additions & 1 deletion platform/pal_uefi/SbsaPalLib.inf
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Expand Up @@ -68,4 +68,3 @@

[BuildOptions]
GCC:*_*_*_ASM_FLAGS = -march=armv8.1-a

4 changes: 1 addition & 3 deletions platform/pal_uefi/src/AArch64/AvsTestInfra.S
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Expand Up @@ -42,8 +42,6 @@ ASM_PFX(UpdateElr):
// <EDK2_PATH>/ArmPkg/Library/ArmExceptionLib/AArch64/ExceptionSupport.S

add x1, x28, #FP_CONTEXT_SIZE
ldr x2, [x1] // Load the stacked ELR into x2
add x2, x2, x0 // Add the offset provided by test to x2
str x2, [x1] // Update the stacked location with offet added ELR
str x0, [x1] // Update the stacked location with user address

ret
32 changes: 32 additions & 0 deletions platform/pal_uefi/src/pal_acpi.c
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Expand Up @@ -157,3 +157,35 @@ pal_get_mcfg_ptr()

}

/**
@brief Iterate through the tables pointed by XSDT and return MCFG Table address
@param None
@return 64-bit SPCR address
**/
UINT64
pal_get_spcr_ptr()
{
EFI_ACPI_DESCRIPTION_HEADER *Xsdt;
UINT64 *Entry64;
UINT32 Entry64Num;
UINT32 Idx;

Xsdt = (EFI_ACPI_DESCRIPTION_HEADER *) pal_get_xsdt_ptr();
if (Xsdt == NULL) {
Print(L"XSDT not found \n");
return 0;
}

Entry64 = (UINT64 *)(Xsdt + 1);
Entry64Num = (Xsdt->Length - sizeof(EFI_ACPI_DESCRIPTION_HEADER)) >> 3;
for (Idx = 0; Idx < Entry64Num; Idx++) {
if (*(UINT32 *)(UINTN)(Entry64[Idx]) == EFI_ACPI_2_0_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE) {
return(UINT64)(Entry64[Idx]);
}
}

return 0;

}
34 changes: 30 additions & 4 deletions platform/pal_uefi/src/pal_gic.c
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Expand Up @@ -124,8 +124,8 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
GicTable->header.num_its++;
GicEntry++;
}
Entry = (EFI_ACPI_6_1_GIC_STRUCTURE *) ((UINT8 *)Entry + (Entry->Length));
Length += Entry->Length;
Entry = (EFI_ACPI_6_1_GIC_STRUCTURE *) ((UINT8 *)Entry + (Entry->Length));


} while(Length < TableLength);
Expand All @@ -135,7 +135,7 @@ pal_gic_create_info_table(GIC_INFO_TABLE *GicTable)
}

/**
@brief Enable the interrupt in the GIC Distributor and GIC CPU Interface and hook
@brief Enable the interrupt in the GIC Distributor and GIC CPU Interface and hook
the interrupt service routine for the IRQ to the UEFI Framework
@param int_id Interrupt ID which needs to be enabled and service routine installed for
Expand Down Expand Up @@ -169,8 +169,34 @@ pal_gic_install_isr(UINT32 int_id, VOID (*isr)())
Status = gInterrupt->RegisterInterruptSource (gInterrupt, int_id, isr); //register our Handler.
//Even if this fails. there is nothing we can do in UEFI mode
}
// Enable the Interrupt
gInterrupt->EnableInterruptSource(gInterrupt, int_id);

return 0;
}

/**
@brief Indicate that processing of interrupt is complete by writing to
End of interrupt register in the GIC CPU Interface
@param int_id Interrupt ID which needs to be acknowledged that it is complete
@return Status of the operation
**/
UINT32
pal_gic_end_of_interrupt(UINT32 int_id)
{

EFI_STATUS Status;

// Find the interrupt controller protocol.
Status = gBS->LocateProtocol (&gHardwareInterruptProtocolGuid, NULL, (VOID **)&gInterrupt);
if (EFI_ERROR(Status)) {
return 0xFFFFFFFF;
}

//
//EndOfInterrupt.
//
gInterrupt->EndOfInterrupt(gInterrupt, int_id);

return 0;
}
Expand Down
6 changes: 3 additions & 3 deletions platform/pal_uefi/src/pal_pe.c
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Expand Up @@ -120,10 +120,10 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable)
PeTable->header.num_of_pe++;
}

Entry = (EFI_ACPI_6_1_GIC_STRUCTURE *) ((UINT8 *)Entry + (Entry->Length));
Length += Entry->Length;
Entry = (EFI_ACPI_6_1_GIC_STRUCTURE *) ((UINT8 *)Entry + (Entry->Length));

}while(Length < TableLength);
}while(Length < TableLength);

pal_pe_data_cache_ci_va((UINT64)PeTable);
PalAllocateSecondaryStack(PeTable->header.num_of_pe);
Expand Down Expand Up @@ -219,7 +219,7 @@ UpdateElr(UINT64 offset);


VOID
pal_pe_increment_elr(UINT64 offset)
pal_pe_update_elr(UINT64 offset)
{
UpdateElr(offset);
}
Expand Down
20 changes: 18 additions & 2 deletions platform/pal_uefi/src/pal_peripherals.c
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Expand Up @@ -22,6 +22,7 @@

#include <Protocol/AcpiTable.h>
#include "Include/IndustryStandard/Acpi61.h"
#include "Include/IndustryStandard/SerialPortConsoleRedirectionTable.h"

#include "include/pal_uefi.h"
#include "include/sbsa_pcie_enum.h"
Expand All @@ -33,12 +34,16 @@
#define BAR1 1
#define BAR2 2

UINT64
pal_get_spcr_ptr();

VOID
pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
{
UINT32 DeviceBdf = 0;
UINT32 StartBdf = 0;
PERIPHERAL_INFO_BLOCK *per_info;
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE *spcr;


per_info = peripheralInfoTable->info;
Expand Down Expand Up @@ -78,10 +83,21 @@ pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *peripheralInfoTable)
per_info++;
//Increment and check if we have more controllers
StartBdf = incrementBusDev(DeviceBdf);
}
}

} while (DeviceBdf != 0);

/* Search for a SPCR table in the system to get the UART details */
spcr = (EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE *)pal_get_spcr_ptr();

if (spcr) {
peripheralInfoTable->header.num_uart++;
per_info->base0 = spcr->BaseAddress.Address;
per_info->irq = spcr->Irq;
per_info->type = PERIPHERAL_TYPE_UART;
per_info++;
}

if (PLATFORM_GENERIC_UART_BASE) {
peripheralInfoTable->header.num_uart++;
per_info->base0 = PLATFORM_GENERIC_UART_BASE;
Expand Down
5 changes: 5 additions & 0 deletions platform/secure_sw/arm-tf/sbsa_acs_platform.h
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Expand Up @@ -32,6 +32,11 @@
#define SBSA_SEC_UART_BASE PLAT_ARM_BL31_RUN_UART_BASE
#define SBSA_SEC_UART_GSIV 0 //148

#define SBSA_TRUSTED_SRAM_BASE1 ARM_TRUSTED_SRAM_BASE + 0x00
#define SBSA_TRUSTED_SRAM_BASE2 ARM_TRUSTED_SRAM_BASE + 0x20
#define SBSA_TRUSTED_SRAM_BASE3 ARM_TRUSTED_SRAM_BASE + 0x40
#define SBSA_TRUSTED_SRAM_BASE4 ARM_TRUSTED_SRAM_BASE + 0x60

/**
@brief PLATFORM FUNCTIONS - Modify this based on the Target Platform
**/
Expand Down
3 changes: 2 additions & 1 deletion platform/secure_sw/arm-tf/sbsa_avs.h
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Expand Up @@ -50,7 +50,8 @@ typedef enum {
SBSA_SECURE_TEST_EL3_PHY,
SBSA_SECURE_TEST_WAKEUP,
SBSA_SECURE_TEST_FINISH,
SBSA_SECURE_INFRA_INIT
SBSA_SECURE_INFRA_INIT,
SBSA_SECURE_PLATFORM_ADDRESS
}SBSA_SECURE_TEST_INDEX_e;

#define SBSA_SECURE_GET_RESULT 0x9000
Expand Down
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