From 77bca2decaf36feb4db154120bd10ccfd645c6f3 Mon Sep 17 00:00:00 2001 From: Blaise Tine Date: Mon, 16 Nov 2020 02:39:53 -0800 Subject: [PATCH] constant integration updates --- .travis.yml | 5 +++-- ci/blackbox.sh | 3 +++ ci/prebuilt.sh | 3 +++ ci/test_driver.sh | 3 +++ ci/test_opencl.sh | 3 +++ ci/test_riscv_isa.sh | 3 +++ ci/test_runtime.sh | 3 +++ ci/toolchain_install.sh | 3 +++ driver/opae/vlsim/Makefile | 2 +- driver/rtlsim/Makefile | 2 +- hw/rtl/cache/VX_bank.v | 4 ++-- 11 files changed, 28 insertions(+), 6 deletions(-) diff --git a/.travis.yml b/.travis.yml index a656a14be..8399f562e 100644 --- a/.travis.yml +++ b/.travis.yml @@ -31,8 +31,9 @@ script: - ci/blackbox.sh -run_2c - ci/blackbox.sh -run_4c - ci/blackbox.sh -run_4c_l2 - - ci/blackbox.sh -run_8c_2l2 - - ci/blackbox.sh -run_16c_4l2_l3 + #- travis_wait 30 ci/blackbox.sh -run_8c_2l2 + #- travis_wait 30 ci/blackbox.sh -run_4c_2l2_l3 + #- travis_wait 30 ci/blackbox.sh -run_8c_4l2_l3 after_success: # Gather code coverage diff --git a/ci/blackbox.sh b/ci/blackbox.sh index 35683fe96..428245f66 100755 --- a/ci/blackbox.sh +++ b/ci/blackbox.sh @@ -1,5 +1,8 @@ #!/bin/sh +# exit when any command fails +set -e + run_1c() { # test single core diff --git a/ci/prebuilt.sh b/ci/prebuilt.sh index 111cd49f4..4198b2e8a 100755 --- a/ci/prebuilt.sh +++ b/ci/prebuilt.sh @@ -1,5 +1,8 @@ #!/bin/bash +# exit when any command fails +set -e + OS_DIR=ubuntu/bionic SRCDIR=/opt DESTDIR=. diff --git a/ci/test_driver.sh b/ci/test_driver.sh index 73e0ae78c..e905104a5 100755 --- a/ci/test_driver.sh +++ b/ci/test_driver.sh @@ -1,3 +1,6 @@ #!/bin/bash +# exit when any command fails +set -e + make -C driver/tests run \ No newline at end of file diff --git a/ci/test_opencl.sh b/ci/test_opencl.sh index 9cb23e8fd..5aadc91fa 100755 --- a/ci/test_opencl.sh +++ b/ci/test_opencl.sh @@ -1,3 +1,6 @@ #!/bin/sh +# exit when any command fails +set -e + make -C benchmarks/opencl run diff --git a/ci/test_riscv_isa.sh b/ci/test_riscv_isa.sh index c22540b6d..4b47b4275 100755 --- a/ci/test_riscv_isa.sh +++ b/ci/test_riscv_isa.sh @@ -1,3 +1,6 @@ #!/bin/bash +# exit when any command fails +set -e + make -C hw/simulate run diff --git a/ci/test_runtime.sh b/ci/test_runtime.sh index 5886e1c2c..3eba41fab 100755 --- a/ci/test_runtime.sh +++ b/ci/test_runtime.sh @@ -1,3 +1,6 @@ #!/bin/bash +# exit when any command fails +set -e + make -C runtime/tests run diff --git a/ci/toolchain_install.sh b/ci/toolchain_install.sh index 996b68e56..36e8ca084 100755 --- a/ci/toolchain_install.sh +++ b/ci/toolchain_install.sh @@ -1,5 +1,8 @@ #!/bin/bash +# exit when any command fails +set -e + REPOSITORY=https://github.com/vortexgpgpu/vortex-toolchain-prebuilt/raw/master riscv() diff --git a/driver/opae/vlsim/Makefile b/driver/opae/vlsim/Makefile index 965fc1475..f1ec24355 100644 --- a/driver/opae/vlsim/Makefile +++ b/driver/opae/vlsim/Makefile @@ -20,7 +20,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += -DDBG_CACHE_REQ_INFO -#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1 +#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 diff --git a/driver/rtlsim/Makefile b/driver/rtlsim/Makefile index acbcfd44e..a6da43902 100644 --- a/driver/rtlsim/Makefile +++ b/driver/rtlsim/Makefile @@ -20,7 +20,7 @@ DBG_PRINT_FLAGS += -DDBG_PRINT_SCOPE DBG_FLAGS += $(DBG_PRINT_FLAGS) DBG_FLAGS += -DDBG_CACHE_REQ_INFO -#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 +#CONFIGS ?= -DNUM_CLUSTERS=2 -DNUM_CORES=4 -DL2_ENABLE=1 -DL3_ENABLE=1 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=4 -DL2_ENABLE=1 CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=2 -DL2_ENABLE=0 #CONFIGS ?= -DNUM_CLUSTERS=1 -DNUM_CORES=1 diff --git a/hw/rtl/cache/VX_bank.v b/hw/rtl/cache/VX_bank.v index 04e7dc4b5..079a842cf 100644 --- a/hw/rtl/cache/VX_bank.v +++ b/hw/rtl/cache/VX_bank.v @@ -860,8 +860,8 @@ module VX_bank #( `ifdef DBG_PRINT_CACHE_BANK always @(posedge clk) begin - if (miss_st3 && (incoming_st0_fill_st3 || incoming_st1_fill_st3 || incoming_st2_fill_st3)) begin - $display("%t: incoming fill - addr=%0h, st0=%b, st1=%b, st2=%b", $time, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), incoming_st0_fill_st3, incoming_st1_fill_st3, incoming_st2_fill_st3); + if (miss_st3 && incoming_fill) begin + $display("%t: incoming fill - addr=%0h, st3=%b, dfp=%b", $time, `LINE_TO_BYTE_ADDR(addr_st3, BANK_ID), incoming_fill_st3, incoming_fill_dfp_st3); assert(!is_msrq_st3); end if (pipeline_stall) begin