diff --git a/rtl/riscv_iommu.sv b/rtl/riscv_iommu.sv
index 39e0b0f..795f540 100644
--- a/rtl/riscv_iommu.sv
+++ b/rtl/riscv_iommu.sv
@@ -773,11 +773,10 @@ module riscv_iommu #(
             .ar_chan_t      ( ar_chan_t     ),
             .r_chan_t       ( r_chan_t      ),
             // AXI request/response
-            .req_t          ( axi_req_t     ),
-            .resp_t         ( axi_rsp_t     ),
+            .axi_req_t      ( axi_req_t     ),
+            .axi_resp_t     ( axi_rsp_t     ),
             .NoMstPorts     ( 2             ),  // MRIF supports adds ignoring mechanism
             .AxiLookBits    ( ID_WIDTH      ),  // Assuming same value as AXI ID width
-            .FallThrough    ( 1'b0          ),
             .SpillAw        ( 1'b0          ),
             .SpillW         ( 1'b0          ),
             .SpillB         ( 1'b0          ),
diff --git a/rtl/software_interface/regmap/rv_iommu_regmap.sv b/rtl/software_interface/regmap/rv_iommu_regmap.sv
index c56e665..48d5996 100644
--- a/rtl/software_interface/regmap/rv_iommu_regmap.sv
+++ b/rtl/software_interface/regmap/rv_iommu_regmap.sv
@@ -3440,6 +3440,6 @@ module rv_iommu_regmap #(
   assign unused_be = ^reg_be;
 
   // Assertions for Register Interface
-  // `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
+  `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
 
 endmodule