diff --git a/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi b/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi
index a2e40c0ddbf09c..ccb952653c0b8c 100644
--- a/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi
+++ b/dts/riscv/espressif/esp32c2/esp32c2_common.dtsi
@@ -56,9 +56,9 @@
 		compatible = "simple-bus";
 		ranges;
 
-		sram0: memory@40370000 {
+		sram0: memory@4037c000 {
 			compatible = "zephyr,memory-region", "mmio-sram";
-			reg = <0x40370000 DT_SIZE_K(16)>;
+			reg = <0x4037c000 DT_SIZE_K(16)>;
 			zephyr,memory-region = "SRAM0";
 		};
 
diff --git a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
index e9e10972b29aea..9f297e97e81e5d 100644
--- a/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
+++ b/dts/riscv/espressif/esp32c3/esp32c3_common.dtsi
@@ -80,9 +80,9 @@
 		compatible = "simple-bus";
 		ranges;
 
-		sram0: memory@40370000 {
+		sram0: memory@4037c000 {
 			compatible = "zephyr,memory-region", "mmio-sram";
-			reg = <0x40370000 DT_SIZE_K(16)>;
+			reg = <0x4037c000 DT_SIZE_K(16)>;
 			zephyr,memory-region = "SRAM0";
 		};
 
diff --git a/soc/espressif/esp32c2/memory.h b/soc/espressif/esp32c2/memory.h
index 5e9db542e46ca3..fbf9a7b8f22bf7 100644
--- a/soc/espressif/esp32c2/memory.h
+++ b/soc/espressif/esp32c2/memory.h
@@ -9,7 +9,7 @@
 #define SRAM0_SIZE         DT_REG_SIZE(DT_NODELABEL(sram0))
 
 /* SRAM1 (256kB) memory */
-#define SRAM1_IRAM_START   (SRAM0_IRAM_START + SRAM0_SIZE)
+#define SRAM1_IRAM_START   (SRAM1_DRAM_START + IRAM_DRAM_OFFSET)
 #define SRAM1_DRAM_START   DT_REG_ADDR(DT_NODELABEL(sram1))
 #define SRAM1_SIZE         DT_REG_SIZE(DT_NODELABEL(sram1))
 
diff --git a/soc/espressif/esp32c3/memory.h b/soc/espressif/esp32c3/memory.h
index 070ca872a314b9..87a832169fc797 100644
--- a/soc/espressif/esp32c3/memory.h
+++ b/soc/espressif/esp32c3/memory.h
@@ -9,7 +9,7 @@
 #define SRAM0_SIZE         DT_REG_SIZE(DT_NODELABEL(sram0))
 /* SRAM1 (384kB) memory */
 #define SRAM1_DRAM_START   DT_REG_ADDR(DT_NODELABEL(sram1))
-#define SRAM1_IRAM_START   (SRAM0_IRAM_START + SRAM0_SIZE)
+#define SRAM1_IRAM_START   (SRAM1_DRAM_START + IRAM_DRAM_OFFSET)
 #define SRAM1_SIZE         DT_REG_SIZE(DT_NODELABEL(sram1))
 /* ICache size is fixed to 16KB on ESP32-C3 */
 #define ICACHE_SIZE        SRAM0_SIZE