From 7e45d78d8ba260c290fe3a74a952dd414f4a3dd5 Mon Sep 17 00:00:00 2001 From: Laurentiu Mihalcea Date: Fri, 25 Oct 2024 15:11:34 +0300 Subject: [PATCH] dts: xtensa: add imx8qm and imx8qxp DTSI variants imx8qm and imx8qxp have a couple of differences regarding the peripheral address spaces and how the DT nodes are configured, which is why using a generic DTSI (nxp_imx8.dtsi) for the both of them is not right. One of the differences between the two, which affects Zephyr is the fact that irqstr's address space is different. Up until now this has been dealt with at the board level (i.e: imx8qxp_mek_mimx8qx6_adsp.dts), which is not right as this is not board-specific, but rather soc-specific. Additionally, this causes the following warning during compilation: "unit address and first address in 'reg' (0x51080000) don't match for /interrupt-controller@510a0000" To fix this, add two new DTSIs: nxp_imx8qm and nxp_imx8qxp. Each board (i.e: imx8qm_mek and imx8qxp_mek) will have to include the DTSI for their soc instead of the generic DTSI (i.e: nxp_imx8). Signed-off-by: Laurentiu Mihalcea --- .../imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts | 2 +- .../imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts | 6 +- dts/xtensa/nxp/nxp_imx8.dtsi | 73 ---------------- dts/xtensa/nxp/nxp_imx8qm.dtsi | 83 +++++++++++++++++++ dts/xtensa/nxp/nxp_imx8qxp.dtsi | 82 ++++++++++++++++++ 5 files changed, 167 insertions(+), 79 deletions(-) create mode 100644 dts/xtensa/nxp/nxp_imx8qm.dtsi create mode 100644 dts/xtensa/nxp/nxp_imx8qxp.dtsi diff --git a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts index 9eddb9385b07fb3..81daabb579f570b 100644 --- a/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts +++ b/boards/nxp/imx8qm_mek/imx8qm_mek_mimx8qm6_adsp.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx8qm_mek_mimx8qm6_adsp-pinctrl.dtsi" / { diff --git a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts index f7b1d061d1a1245..460ca19029c2a08 100644 --- a/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts +++ b/boards/nxp/imx8qxp_mek/imx8qxp_mek_mimx8qx6_adsp.dts @@ -6,7 +6,7 @@ /dts-v1/; -#include +#include #include "imx8qxp_mek_mimx8qx6_adsp-pinctrl.dtsi" / { @@ -31,7 +31,3 @@ pinctrl-0 = <&sai1_default>; pinctrl-names = "default"; }; - -&irqsteer { - reg = <0x51080000 DT_SIZE_K(64)>; -}; diff --git a/dts/xtensa/nxp/nxp_imx8.dtsi b/dts/xtensa/nxp/nxp_imx8.dtsi index 5402e678525f9c4..687f50a69805436 100644 --- a/dts/xtensa/nxp/nxp_imx8.dtsi +++ b/dts/xtensa/nxp/nxp_imx8.dtsi @@ -32,79 +32,6 @@ }; }; - irqsteer: interrupt-controller@510a0000 { - compatible = "nxp,irqsteer-intc"; - reg = <0x510a0000 DT_SIZE_K(64)>; - power-domains = <&irqstr_pd>; - - #size-cells = <0>; - #address-cells = <1>; - - master0: interrupt-controller@0 { - compatible = "nxp,irqsteer-master"; - reg = <0>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts-extended = <&clic 19 0 0>; - }; - - master1: interrupt-controller@1 { - compatible = "nxp,irqsteer-master"; - reg = <1>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts-extended = <&clic 20 0 0>; - }; - - master2: interrupt-controller@2 { - compatible = "nxp,irqsteer-master"; - reg = <2>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts-extended = <&clic 21 0 0>; - }; - - master3: interrupt-controller@3 { - compatible = "nxp,irqsteer-master"; - reg = <3>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts-extended = <&clic 22 0 0>; - }; - - master4: interrupt-controller@4 { - compatible = "nxp,irqsteer-master"; - reg = <4>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts-extended = <&clic 23 0 0>; - }; - - master5: interrupt-controller@5 { - compatible = "nxp,irqsteer-master"; - reg = <5>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts-extended = <&clic 24 0 0>; - }; - - master6: interrupt-controller@6 { - compatible = "nxp,irqsteer-master"; - reg = <6>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts-extended = <&clic 25 0 0>; - }; - - master7: interrupt-controller@7 { - compatible = "nxp,irqsteer-master"; - reg = <7>; - interrupt-controller; - #interrupt-cells = <1>; - interrupts-extended = <&clic 26 0 0>; - }; - }; - sram0: memory@92400000 { device_type = "memory"; compatible = "mmio-sram"; diff --git a/dts/xtensa/nxp/nxp_imx8qm.dtsi b/dts/xtensa/nxp/nxp_imx8qm.dtsi new file mode 100644 index 000000000000000..a5e5b7ceaac39d0 --- /dev/null +++ b/dts/xtensa/nxp/nxp_imx8qm.dtsi @@ -0,0 +1,83 @@ +/* + * Copyright 2021, 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + + +#include + +/ { + irqsteer: interrupt-controller@510a0000 { + compatible = "nxp,irqsteer-intc"; + reg = <0x510a0000 DT_SIZE_K(64)>; + power-domains = <&irqstr_pd>; + + #size-cells = <0>; + #address-cells = <1>; + + master0: interrupt-controller@0 { + compatible = "nxp,irqsteer-master"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 19 0 0>; + }; + + master1: interrupt-controller@1 { + compatible = "nxp,irqsteer-master"; + reg = <1>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 20 0 0>; + }; + + master2: interrupt-controller@2 { + compatible = "nxp,irqsteer-master"; + reg = <2>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 21 0 0>; + }; + + master3: interrupt-controller@3 { + compatible = "nxp,irqsteer-master"; + reg = <3>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 22 0 0>; + }; + + master4: interrupt-controller@4 { + compatible = "nxp,irqsteer-master"; + reg = <4>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 23 0 0>; + }; + + master5: interrupt-controller@5 { + compatible = "nxp,irqsteer-master"; + reg = <5>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 24 0 0>; + }; + + master6: interrupt-controller@6 { + compatible = "nxp,irqsteer-master"; + reg = <6>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 25 0 0>; + }; + + master7: interrupt-controller@7 { + compatible = "nxp,irqsteer-master"; + reg = <7>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 26 0 0>; + }; + }; +}; diff --git a/dts/xtensa/nxp/nxp_imx8qxp.dtsi b/dts/xtensa/nxp/nxp_imx8qxp.dtsi new file mode 100644 index 000000000000000..ff3e30a297abfb0 --- /dev/null +++ b/dts/xtensa/nxp/nxp_imx8qxp.dtsi @@ -0,0 +1,82 @@ +/* + * Copyright 2021, 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +/ { + irqsteer: interrupt-controller@51080000 { + compatible = "nxp,irqsteer-intc"; + reg = <0x51080000 DT_SIZE_K(64)>; + power-domains = <&irqstr_pd>; + + #size-cells = <0>; + #address-cells = <1>; + + master0: interrupt-controller@0 { + compatible = "nxp,irqsteer-master"; + reg = <0>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 19 0 0>; + }; + + master1: interrupt-controller@1 { + compatible = "nxp,irqsteer-master"; + reg = <1>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 20 0 0>; + }; + + master2: interrupt-controller@2 { + compatible = "nxp,irqsteer-master"; + reg = <2>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 21 0 0>; + }; + + master3: interrupt-controller@3 { + compatible = "nxp,irqsteer-master"; + reg = <3>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 22 0 0>; + }; + + master4: interrupt-controller@4 { + compatible = "nxp,irqsteer-master"; + reg = <4>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 23 0 0>; + }; + + master5: interrupt-controller@5 { + compatible = "nxp,irqsteer-master"; + reg = <5>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 24 0 0>; + }; + + master6: interrupt-controller@6 { + compatible = "nxp,irqsteer-master"; + reg = <6>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 25 0 0>; + }; + + master7: interrupt-controller@7 { + compatible = "nxp,irqsteer-master"; + reg = <7>; + interrupt-controller; + #interrupt-cells = <1>; + interrupts-extended = <&clic 26 0 0>; + }; + }; +};